For debugging a MMU related issue with Cortex-A5 core, I dumped TLB by following instruction from DDI0433C_cortex_a5_trm.pdf, chapter 7.6, and I think that I successfully got the TLB raw data. Based on table Table 7-7 TLB descriptor format in the same document, I can match bits like TEX, AP, Bufferable, Cacheable, Shareable and so on, but I'm not very clear about the 15 bits VA and 20 bits PA. Since VA in TLB is just 15 bits. For small page, we would need 20 bits VA. So how should I decode the VA in TLB? I guess the TLB entry index would be used for decoding the VA address. But I not find exact mapping. In one case, I believe the VA is is 0xB2000, and in TLB dump, it is the entry with index 0x32, the 15 bits VA field has value as 5. Trying to figure out how to decode the VA value 5, with index 0x32, to get the VA address 0xB2000. Anyone knows any detail about this? Thanks in advance.
What is the page attribute of the page that VA=0xB2000 resides? You need to figure the page size first.
Each page size will have different decoding. For example, if it is 4K small page, the VA offset = 2^12, which is exactly the same as 2^12 of PA.
For 1MB section page, the VA offset = 2^20.
I have already mentioned it is a small page, and know I would need to know the higher 20 bits of the 32 bits address. So that is not the question. The question is the entry only contains 15 bits, and how to decode this 15 bits to the 20 bits of the VA. ARM support did give me some feedback on this, and confirmed the index does need to be taken in count for decoding.