Instruction Cache Throttle PMU event

I am looking for information on the Instruction Cache Throttle event on Cortex-A53. The docs just say "Instruction Cache Throttle occurred". Can anyone elaborate or point me to a more thorough explanation? Internet searching has not turned up anything.

In some cases, we see tens of thousands of these events after execution of a tight loop reading a 32KB array. The amount of these events strongly correlates with the execution time of the loop.

Thanks.