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Instruction Cache Throttle PMU event

phxeng

I am looking for information on the Instruction Cache Throttle event on Cortex-A53. The docs just say "Instruction Cache Throttle occurred". Can anyone elaborate or point me to a more thorough explanation? Internet searching has not turned up anything.

In some cases, we see tens of thousands of these events after execution of a tight loop reading a 32KB array. The amount of these events strongly correlates with the execution time of the loop.

Thanks.

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    I have the same problem with facing same issue but no response from anyone and couldn't find this topic troubleshooting in search engine.  My Indigo Card

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    Hi ,

    Instruction cache throttle is an optimisation preventing fetches, which would likely be wasted. When you see the cache throttle events occurring it means the optimisation is actually taking place. This is good as it saves power and does not affect functionality.

    If you want to experiment, this optimisation can be enabled/disabled with CPUACTLR_EL1.IFUTHDIS.

    Best regards,

    Vincent.