This is not a Big.little question - this is for non homogeneous cores with possibly different instruction sets, and different schedulers (different OSs on each core).
What does system memory look like from a heterogenous chip that is ARM A/R or ARM A/M?
Is it or can it be shared based on physical address range segmentation?
Can memory be shared between different core types (Same Memory/Flash Chip, but with internal bus managed by the mixed core HW).
I have seen some examples of this but have not seen HW application notes for mixed core usage of RAM.
Basically, what does the bus architecture look like, and can you direct me to relevant HW/SW application notes?
I'm not sure that I can give a general answer to this, as different processors support different bus architectures. For example, Cortex-M4 uses AHB-Lite, whereas Cortex-M7 has AXI.
https://developer.arm.com/documentation/ddi0439/b/Functional-Description/Interfaces/Bus-interfaceshttps://developer.arm.com/documentation/ddi0489/f/introduction/component-blocks/memory-system
Furthermore different devices will be configured in different ways - you may have a completely shared memory system, or there may be certain addresses (or peripherals) which are only accessible by a given processor.
Are you looking to design your own SoC, or are you using standard microcontrollers? You may wish to look at some of the devices on the market today, for example:
https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.htmlhttps://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-7-processors:IMX7-SERIES
Hope this helps, Ronan