How many clock cycles does it take to switch working states by CPS #n

I think you want this section of the Cortex-R5's Technical Reference Manual (TRM):

https://developer.arm.com/documentation/ddi0460/d/Cycle-Timings-and-Interlock-Behavior/Processor-state-updating-instructions?lang=en

But note there's more to it than just the cycles needed by the core.  There's the dual issue rules (https://developer.arm.com/documentation/ddi0460/d/Cycle-Timings-and-Interlock-Behavior/Dual-issue?lang=en), whether you hit/miss in the cache, etc...

I think you want this section of the Cortex-R5's Technical Reference Manual (TRM):

https://developer.arm.com/documentation/ddi0460/d/Cycle-Timings-and-Interlock-Behavior/Processor-state-updating-instructions?lang=en

But note there's more to it than just the cycles needed by the core.  There's the dual issue rules (https://developer.arm.com/documentation/ddi0460/d/Cycle-Timings-and-Interlock-Behavior/Dual-issue?lang=en), whether you hit/miss in the cache, etc...