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The system has been set up to be software coherent. A single coherent domain contains two A15 cores and L2. When cores 0 and 1 are reading/writing the same cache line, what happens if core 0 does a cache flush / invalidate on that cache line?
Meant to add:For the full technical explanation, you want "Requirements for cache and branch predictor maintenance operations" in section B2.2.7 of the Armv7-A Architecture Reference Manual.ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition