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The system has been set up to be software coherent. A single coherent domain contains two A15 cores and L2. When cores 0 and 1 are reading/writing the same cache line, what happens if core 0 does a cache flush / invalidate on that cache line?
Partly depends on what you mean by broadcast.In a strict sense, "no". Some operations can be broadcast (such as TLB invalidates), but data cache ops like this are not.However, data cache operations by one core affect other core(s) due to the coherency rules (subject to factors such as the Shareability and which domain each core is in). So in the example above, the DCCIMVAC would affect both core 0 and core 1, because its an operation on a shareable address and both cores are in the same inner shareable domain.
One way to think of this is that D cache ops are sort of data memory accesses. If an equivalent STR would be coherent, then D cache op will also be coherent. It's not a perfect analogy, but its helped me.
Note: This doesn't apply to Set/Way operations, for which the rules are different.
Meant to add:For the full technical explanation, you want "Requirements for cache and branch predictor maintenance operations" in section B2.2.7 of the Armv7-A Architecture Reference Manual.ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
Thanks! Your analogy makes perfect sense.