Hi,
I try to configure GIC interrupt controller on a cortex R52 multicore setup to be able to receive SPI interrupts on all available cores.
Interrupt handling works fine as long as all interrupts are routed to core 0 (I assume routing to core 0 is the default).
Interrupt routing is done by setting GICD_IROUTER<n> registers of the source.
In GIC distributor ARE_S bit is set in GICD_CTLR register, so affinity routing is active for secure state.
Interrupts to be tested are triggered by directly writing to corresponding bit of GICD_ISPENDR<n> register.
When triggering interrupt source to be processed on core 1 pending flag in GIC Distributor is set, yet GIC CPU interface of core 1 does not show any pending interrupt source.
GICC_PMR of core 1 is set to allow all priorities.
Are there any other modules to check to see why interrupt is not routed correctly to the PE?
Thanks,
Lukas
More: Did you double-check the right target register is set? (vector +32 or -32?!)
CPU interface is enabled on the second core. I get timer interrupts on this core (interrupt source 30).
Target register should be correct, I can trigger the source just fine on core 0 (using the same code, without setting IROUTER register of course).