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How writing ICC_EOIR1_EL1 works for Group 1 Interrupts when running on EL3 in GICv3?

MHesham

Hi,

I have a question regarding how an ARMv8A core would handle a Group1 interrupt when it is running in EL3.

The GICv3/v4 Arch. Document states the following:

- A write to ICC_EOIR1_EL1 performs a priority drop for Non-secure Group 1 interrupts, if the PE is
operating in Non-secure state or at EL3.
- When operating in Secure state, a write to ICC_EOIR1_EL1 performs a priority drop for Secure Group 1
interrupts.

The first sentence implies that a core operating in EL3 would handle(perform a priority drop) a Group1 Non secure interrupt.
In the second sentence that operating in secure state would perform a priority drop.

Does the secure state in the second sentance implies EL-S only or does it include EL3 too? In another way is operating in EL3 able to handle both secure and non-secure interrupts. or Non-secure only?

Thanks.

Parents
  • +1

    The answer can be found in GICv3/v4 spec in section "13.1.3 aarch64/support/ICC_EOIR1_EL1" pseudo-code for handling the register. It says:

    elsif pGroup == IntGroup_G1NS && (IsEL3OrMon() || !IsSecure()) then
  // Highest priority is Non-Secure Group 1
  // Drop the priority
  boolean dropped = PriorityDrop[ICC_AP1R_EL1NS];


elsif pGroup == IntGroup_G1S && IsSecure() then
  // Highest priority is Secure Group 1 and we are secure
  // Drop the priority
  boolean dropped = PriorityDrop[ICC_AP1R_EL1S];

    That is, when the (highest priority active) interrupt is a G1NS, the priority is dropped if the CPU is at EL3/MON or if it is in a non-secure state.

    Similarly, when the interrupt is a G1S, the priority is dropped if the CPU is in a secure-state. The pseudo-code for IsSecure() is found inside the armv8 manual - the secure state includes EL3 along with secure levels below EL3.

    EL3 can perform the priority drop for secure or non-secure G1 interrupt, provided that such an interrupt is routed to EL3. The section "D1.13.1 Asynchronous exception routing" in the armv8 manual has details about the interrupt routing under various configuration options.

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  • +1

    The answer can be found in GICv3/v4 spec in section "13.1.3 aarch64/support/ICC_EOIR1_EL1" pseudo-code for handling the register. It says:

    elsif pGroup == IntGroup_G1NS && (IsEL3OrMon() || !IsSecure()) then
  // Highest priority is Non-Secure Group 1
  // Drop the priority
  boolean dropped = PriorityDrop[ICC_AP1R_EL1NS];


elsif pGroup == IntGroup_G1S && IsSecure() then
  // Highest priority is Secure Group 1 and we are secure
  // Drop the priority
  boolean dropped = PriorityDrop[ICC_AP1R_EL1S];

    That is, when the (highest priority active) interrupt is a G1NS, the priority is dropped if the CPU is at EL3/MON or if it is in a non-secure state.

    Similarly, when the interrupt is a G1S, the priority is dropped if the CPU is in a secure-state. The pseudo-code for IsSecure() is found inside the armv8 manual - the secure state includes EL3 along with secure levels below EL3.

    EL3 can perform the priority drop for secure or non-secure G1 interrupt, provided that such an interrupt is routed to EL3. The section "D1.13.1 Asynchronous exception routing" in the armv8 manual has details about the interrupt routing under various configuration options.

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