DIC/IDC bit in CTR

digital_kevin said:

Can I say that  DCache clean will not be needed for any cache coherency situation since the hardware will do it when IDC = 1?

One cannot say that.

The IDC/DIC facility is limited to establishing coherency between the DCache and the ICache. The facility does not dictate rules for other  situations dealing with coherency.

For e.g., when cacheable data is to be read by a device through DMA, it is typically required to clean the data cache upto the PoC, so that the device reads the updated data and not the stale data. The IDC bit does not cast influence over this coherency situation (unless, for instance, PoC is the same as PoU, etc.).

digital_kevin said:

Can I say that  DCache clean will not be needed for any cache coherency situation since the hardware will do it when IDC = 1?

One cannot say that.

The IDC/DIC facility is limited to establishing coherency between the DCache and the ICache. The facility does not dictate rules for other  situations dealing with coherency.

For e.g., when cacheable data is to be read by a device through DMA, it is typically required to clean the data cache upto the PoC, so that the device reads the updated data and not the stale data. The IDC bit does not cast influence over this coherency situation (unless, for instance, PoC is the same as PoU, etc.).

42Bastian Schick is correct.

The situation also arises in case of dynamic compilation (C#, or emulation/virtualization like QEMU), or in case of debugging (setting a breakpoint usually requires modifying the instruction stream).