Hello,
In armv8 Spec, CTR_EL0.DIC/IDC is described as follows:
I really don't get the point of the two bits.
Can someone give me a scenario to explain how the two bits affect？
really appreciated.
I have read the linux code.
Can I say that DCache clean will not be needed for any cache coherency situation since the hardware will do it when IDC = 1?
digital_kevin said:Can I say that DCache clean will not be needed for any cache coherency situation since the hardware will do it when IDC = 1?
One cannot say that.
The IDC/DIC facility is limited to establishing coherency between the DCache and the ICache. The facility does not dictate rules for other situations dealing with coherency.
For e.g., when cacheable data is to be read by a device through DMA, it is typically required to clean the data cache upto the PoC, so that the device reads the updated data and not the stale data. The IDC bit does not cast influence over this coherency situation (unless, for instance, PoC is the same as PoU, etc.).
Thank your for the detailed reply.
So the key point is DCache and ICache coherency. It seems that this kind of coherency is not common.
Except self-modifying code, is there any other DCache-ICache coherency situation we should pay attention to?
I would say moving code from disk to RAM is such a situation.
42Bastian Schick is correct.
The situation also arises in case of dynamic compilation (C#, or emulation/virtualization like QEMU), or in case of debugging (setting a breakpoint usually requires modifying the instruction stream).