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cortex-m55 default address map

sandtrip

I understand cortex-m55 default address map suggests the following possible address range where possibly Code can be fetched from

0x00000000-0x1FFFFFFF Code All accesses are performed on the Instruction Tightly Coupled Memory (ITCM) or Master-AXI (M-AXI) interface.

That suggests the bootcode (starting from reset vector where VTOR points to) and other initial code must be either placed with in this address range Or in the ITCM?

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    Hi Sandtrip,

    The default boot vector address (which is also the Vector Table offset address) is 0x00000000, which can be accessed by the either ITCM interface (if enabled) or via the M-AXI if the ITCM is disabled. There is a way to enable/disable the ITCM out of reset by tying INITTCMEN[0] to the appropriate value.

    The Cortex-M55 has two input signals called, INITSVTOR and INITNSVTOR, that are used to set the vector table addresses in memory for Secure and Non-secure, respectively. INITSVTOR[31:7] is sampled at reset, and clearly must be stable at reset because it drives the very first step of processor initialization, which affects the address from where the processor loads the MSP value and PC value.

    Please note both vector tables and the code need to be in Normal Memory as the Peripheral region is expected to be eXecute Never(XN).

    Thanks,

    Mahmood.

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  • 0

    Hi Sandtrip,

    The default boot vector address (which is also the Vector Table offset address) is 0x00000000, which can be accessed by the either ITCM interface (if enabled) or via the M-AXI if the ITCM is disabled. There is a way to enable/disable the ITCM out of reset by tying INITTCMEN[0] to the appropriate value.

    The Cortex-M55 has two input signals called, INITSVTOR and INITNSVTOR, that are used to set the vector table addresses in memory for Secure and Non-secure, respectively. INITSVTOR[31:7] is sampled at reset, and clearly must be stable at reset because it drives the very first step of processor initialization, which affects the address from where the processor loads the MSP value and PC value.

    Please note both vector tables and the code need to be in Normal Memory as the Peripheral region is expected to be eXecute Never(XN).

    Thanks,

    Mahmood.

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