1. I READ the cortex-a78 trm, i confuse with the L1 Cache, what is VIPT behaves as PIPT? if L1 Cache is VIPT, Can it be understood as On a memory access operation, core get the physical addresses from L1 Cache first, if it do not hit ,than find the MMU?
2. what is the cache means? is it a contains L1 L2 L3 cache?
thanks, when the cache size is big than page size; i found i can use page coloring to resolve;
i found Page-based hardware attributes(PBHA) in MMU in the cortex-a78 trm, does it can solve this problem?
No PBHA is not relevant to VIPT or PIPT, it is an CPU implementation defined behavior for system usage, which is decided by SoC designer
thanks very much