Hi, A few months ago I managed to find the appropriate patent as regards to the single-cycle multiply that is optional on the M0 & M0+. I've just spent 4 fruitless hours searching. IF I cannot get an MP3 decoder running on a 48MHz M0+ I might have to develop on an M1 to which a MULHS instruction is added. I seem to remember that it was either a ripple multiplier or a combinational logic multiplier. I noted that it uses around 8000 extra gates so I am guessing that it's actually 8192? A nice round hex number. Of course, I will also have to learn Verilog so I have ordered a couple of boks.Many thanks,Sean
" I noted that it uses around 8000 extra gates so I am guessing that it's actually 8192?"
No, I would be quite surprised if the number was a power of 2.
In Verilog/VHDL/whatever you can make numbers as wide as you want. It is very common to make structures using varying bit counts.
For example, if you were making an adding tree to add together 4x 4-bit numbers A, B, C, D you might make a structure like this (pseudocode)
4-bit numbers A, B, C, D
5-bit numbers: E, F
6-bit number: Output
E=A + B
F=C + D
Output=E + F