This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Patent of ARM's single-cycle multiply on the M0+?

Hi,
    A few months ago I managed to find the appropriate patent as regards to the single-cycle multiply that is optional on the M0 & M0+. I've just spent 4 fruitless hours searching. IF I cannot get an MP3 decoder running on a 48MHz M0+ I might have to develop on an M1 to which a MULHS instruction is added. I seem to remember that it was either a ripple multiplier or a combinational logic multiplier. I noted that it uses around 8000 extra gates so I am guessing that it's actually 8192? A nice round hex number. 

Of course, I will also have to learn Verilog so I have ordered a couple of boks.

Many thanks,
Sean