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hi. i wonder AMBA 3.0 AXI out-of order - WID & RID

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.

Firstly, i very wonder AWID, WID and BID when write transaction is started.

We assume that two masters(M0, M1-1bit ) and two slave(S0, S1) are. 

The M0 master want to send the burst data to the S0 slave. the M0 master can generate the AWID( value : 0x0001 ). at that time, the M0 master must generate the WID corresponding AWID. I wonder this situation. is the WID value? simply, does the WID value have the same AWID value ( 0x0001) ? also, is the RID value? similarly, does the RID value have the same AWID value ( 0x0001) ?




Secondly, we assume that burst transaction is started.

Do WID and RID have to be generated whenever one of burst data is transferred or only one about all of the burst ?

I totally want to know about the situation.

Parents
  • Hello anytime2736,

    firstly, i very wonder AWID, WID and BID when write transaction is started.

    we assume that two masters(M0, M1-1bit ) and two slave(S0, S1) are. 

    The M0 master want to send the burst data to the S0 slave. the M0 master can generate the AWID( value : 0x0001 ). at that time, the M0 master must generate the WID corresponding AWID. I wonder this situation. is the WID value? simply, does the WID value have the same AWID value ( 0x0001) ?



    First of all, AXI has the multi-layer bus scheme and almost all timing charts are the views by a slave.

    The slave will receive several couples of transaction from several masters.

    The IDs are needed to distinguish every transaction.

    Therefore the AWID, WID and BID should be the same.

    For example the following case would be considered.







    also, is the RID value?

    What is the purpose of the question?

    ARID and RID should be the same to distinguish the data corresponding to its address.

    AWID and ARID might not be the same.

    However the read and the write are independent.


    similarly, does the RID value have the same AWID value ( 0x0001) ?


    The read channel and the write channel are independent and (ARID, RID) may not be the same as (AWID, WID and BID).


    secondly, we assume that burst transaction is started.

    Do WID and RID have to be generated whenever one of burst data is transferred or only one about all of the burst ?


    WID and RID have to be generated whenever one of burst data is transferred because the issued WDATAs or RDATA responces woulld out-of-order.


    I hope my answers will match your intention.


    Best regards,

    Yasuhiko Koumoto.


Reply
  • Hello anytime2736,

    firstly, i very wonder AWID, WID and BID when write transaction is started.

    we assume that two masters(M0, M1-1bit ) and two slave(S0, S1) are. 

    The M0 master want to send the burst data to the S0 slave. the M0 master can generate the AWID( value : 0x0001 ). at that time, the M0 master must generate the WID corresponding AWID. I wonder this situation. is the WID value? simply, does the WID value have the same AWID value ( 0x0001) ?



    First of all, AXI has the multi-layer bus scheme and almost all timing charts are the views by a slave.

    The slave will receive several couples of transaction from several masters.

    The IDs are needed to distinguish every transaction.

    Therefore the AWID, WID and BID should be the same.

    For example the following case would be considered.







    also, is the RID value?

    What is the purpose of the question?

    ARID and RID should be the same to distinguish the data corresponding to its address.

    AWID and ARID might not be the same.

    However the read and the write are independent.


    similarly, does the RID value have the same AWID value ( 0x0001) ?


    The read channel and the write channel are independent and (ARID, RID) may not be the same as (AWID, WID and BID).


    secondly, we assume that burst transaction is started.

    Do WID and RID have to be generated whenever one of burst data is transferred or only one about all of the burst ?


    WID and RID have to be generated whenever one of burst data is transferred because the issued WDATAs or RDATA responces woulld out-of-order.


    I hope my answers will match your intention.


    Best regards,

    Yasuhiko Koumoto.


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