I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.
I tried -mfpu = neon but compiler is not recognizing it. So, what are the possible optimization option available for my application setting. I am using Xilinx SDK IDE for my application.
Hi,
Thanks for your input. I used some of the options but my compiler is not recognizing some options. For example, I used
5557.optimizationOption.pdf
make all 'Building file: ../ti_src/rl_controller.c' 'Invoking: ARM v8 gcc compiler' aarch64-none-elf-gcc -DZF_B2 -Wall -O3 -mfpu=neon-fp-armv8 -g3 -I"D:\docs\sw_backup-5-03-2020\app\inc" -I"D:\docs\sw_backup-5-03-2020\app\src\architecture" -I"C:\Xilinx\SDK\2019.1\data\embeddedsw\lib\bsp\standalone_v6_8\src\arm\cortexa53\64bit" -I"C:\Xilinx\SDK\2019.1\gnu\aarch64\nt\aarch64-none\aarch64-none-elf\include" -I"D:\docs\sw_backup-5-03-2020\zf_b-2_freertos_bsp\psu_cortexa53_0\include" -I"D:\docs\sw_backup-5-03-2020\app\testdata" -I../../zf_b-2_freertos_bsp/psu_cortexa53_0/include -c -fmessage-length=0 -MT"ti_src/rl_controller.o" -MMD -MP -MF"ti_src/rl_controller.d" -MT"ti_src/rl_controller.o" -o "ti_src/rl_controller.o" "../ti_src/rl_controller.c" aarch64-none-elf-gcc: error: unrecognized command line option '-mfpu=neon-fp-armv8' make: *** [ti_src/subdir.mk:32: ti_src/rl_controller.o] Error 1
If I use -mfpu=vFPv4 or -mfloat-abi=hard, compiler still not recognizing it. I would like to use floating point ABI for hardware linkages.
-mfloat-abi=hard
I set the Xilinx SDK with the following settings:
NEON is active by default. Same for FPU.You can tell gcc not to use FPU registers: -mgeneral-regs-only
Thanks for the input. But what about floating-point ABI? How can I enable it to -mfloat-abi=hard because compiler is not recognizing it. I would highly appreciate if you can comment on this.
If you look at the assembly, you will see: It is on by default.
int res(float a, float b) { return (int)(a+b); }
Compile with -O
.arch armv8-a .file "calling.c" .text .align 2 .global res .type res, %function res: fadd s0, s0, s1 fcvtzs w0, s0 ret .size res, .-res
Hello Bastian. This compilation argument is not recognized by the arm-none-eabi-gcc compiler for Cortex A9 (armv7-a). Is it only supported for ARMv8?
By the way if the compiler prevents accesses to FPU registers, does that conflict with compiling with mfpu=vfpv3 and mfloat-abi=hard arguments?
Regards,
Florian
gcc 9.1.0
Guess that answers your question:
arm-none-eabi-gcc -mgeneral-regs-only -march=armv7-a -mfpu=vfpv3 -S float.c -mfloat-abi=hard float.c: In function 'res': float.c:1:5: error: argument of type 'float' not permitted with -mgeneral-regs-only 1 | int res(float a, float b) | ^~~
btw: *gcc -target-help lists all options.
Hello;
Thank you a lot for your inputs. Actually I did not have this option, that's why I asked.
I used gcc 5.4.1, gcc 7.2 and gcc 8.2.0, but the -mgeneral-regs-only never appears. Maybe it's only available for gcc 9.1.0 and above