Hello,
I am working with TI's TMS570LS3137 (ARM Cortex R4F).
A certain part of my code consistently causes a prefetch abort (I say part because the exact location seems to vary slightly).
To try and identify the cause I set a breakpoint at the prefetch abort handler (0x0000000C) and looked at the following registers:
Here is how I disabled parity/ECC check:
// Disable CPU parity/ECC check asm(" PUSH {r1}"); asm(" MRC p15, #0, r1, c1, c0, #1"); // Read ACTLR asm(" BIC r1, r1, #0x0E000000"); // Clear ATCMPCEN, B0TCMPCEN, B1TCMPCEN asm(" MCR p15, #0, r1, c1, c0, #1"); // Write ACTLR asm(" POP {r1}");
These observations leave me with two questions:
Thank you in advance
Thank you for your replies.
It turns out the root cause was not ECC.
Some background: I was working on a bootloader and the abort often occured during erasing of flash. I ultimately fixed the problem by disabling interrupts before erasing. I suspect that interrupts occured during erasing which then caused an instruction fetch from 0x00000018 (IRQ vector). This address is mapped to the same flash bank that was being erased. According to the documentation of the flash controller it is not allowed to execute from a bank while it is being erased. I think that this ultimately caused the prefetch abort.
The fact that the IFSR reported a Synchronous Parity/ECC error is puzzling, but I can live with it, since I was able to fix the problem :^)