We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello,
I am working with TI's TMS570LS3137 (ARM Cortex R4F).
A certain part of my code consistently causes a prefetch abort (I say part because the exact location seems to vary slightly).
To try and identify the cause I set a breakpoint at the prefetch abort handler (0x0000000C) and looked at the following registers:
Here is how I disabled parity/ECC check:
// Disable CPU parity/ECC check asm(" PUSH {r1}"); asm(" MRC p15, #0, r1, c1, c0, #1"); // Read ACTLR asm(" BIC r1, r1, #0x0E000000"); // Clear ATCMPCEN, B0TCMPCEN, B1TCMPCEN asm(" MCR p15, #0, r1, c1, c0, #1"); // Write ACTLR asm(" POP {r1}");
These observations leave me with two questions:
Thank you in advance
Little unrelated, but: You should not use multiple asm() statements if you want the code be placed the way you wrote it:
asm(" PUSH {r1}\n" " MRC p15, #0, r1, c1, c0, #1\n" /* Read ACTLR */ " BIC r1, r1, #0x0E000000\n" /* Clear ATCMPCEN, B0TCMPCEN, B1TCMPCEN */ " MCR p15, #0, r1, c1, c0, #1\n" /* Write ACTLR */ " POP {r1}");