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LDREX/STREX on the M3,M4,M7

Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex (or at most 32 if you can bit map them?). 

Thus it does not seem to be a very practical solution for an RTOS, or am I missing something? 

Parents
  • The chance that an interrupt/exception happens between the LDREX/STREX will increase dramatically while you are the use of it for a mutex with a spin wait on a lock. Especially the code can be spinning on round ~10 instructions and if their is one CMP among LDREX and STREX.
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  • The chance that an interrupt/exception happens between the LDREX/STREX will increase dramatically while you are the use of it for a mutex with a spin wait on a lock. Especially the code can be spinning on round ~10 instructions and if their is one CMP among LDREX and STREX.
Children