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The System Control Processor (SCP) is a dedicated processor that is used to abstract power and system management tasks away from Application Processors (APs). The SCP Firmware provides a software reference implementation for the SCP on the Arm Total Compute Platform.
The primary services of the SCP firmware include:
Using the Power Policy Unit (PPU), it manages power domain modes in accordance with the constraints of System Control and Management Interface (SCMI) commands that request changes in core, cluster, device, and SoC power states.
Responds to SCMI commands, and manages clock and voltage supplies.
The SCP is responsible for configuring the system to allow the Application processor to boot.
Respond to system events, such as GIC wake requests, local timer events, always-on domain wake requests, debug power requests, and watchdog expiration.
On the Total Compute platform, the SCP firmware consists of ROM firmware (SCP BL1) and RAM firmware (SCP BL2). The SCP BL1 firmware is responsible for configuring the entire system and subsequently powering up the main CPU core of the AP. The SCP BL2 firmware serves as the runtime firmware for the SCP, implementing the main features and functionalities of the SCP.
This guide describes:
This guide assumes that you already set up the debugging environment as described in the Guide to Set Up Debugging Environment for Total Compute Software Stack.
The guidance given in this guide is based on the Total Compute TC2-2023.10.04 code.Note: Future code updates might introduce changes, so the guidance might not apply to all cases.
This guide includes the following sections:
The Guide to Set Up Debugging Environment for Total Compute Software Stack describes how to set up the Total Compute debugging environment in Arm DS.
There are some considerations to be aware of when setting up the Total Compute debugging environment.
Step 1: Select Cortex-M3 as your target as follows, when debugging the SCP.
Step 2: Enable debug symbol table file, based on the firmware image you want to debug
By default, however, the SCP firmware is compiled without debug symbol tables. Therefore, the following modifications are necessary to enable the debug symbol tables:
build-scripts:diff --git a/config/common.config b/config/common.config index a99008c..032e3ea 100644 --- a/config/common.config +++ b/config/common.config @@ -23,9 +23,9 @@ CMAKE=${TOOLS_DIR}/cmake-3.22.4-linux-x86_64/bin/cmake SCP_OUTDIR=$OUTPUT_DIR/tmp_build/scp/ SCP_SRC=$SRC_DIR/SCP-firmware SCP_LOG_LEVEL="INFO" -SCP_BUILD_RELEASE=1 +SCP_BUILD_RELEASE=0 SCP_COMPILER=$ARM_BARE_METAL/arm-none-eabi -SCP_BUILD_MODE="release" +SCP_BUILD_MODE="debug" SCP_PLATFORM_VARIANT_STD=0 SCP_PLATFORM_VARIANT_EXPERIMENT=1 SCP_PLATFORM_VARIANT_MPMM=2 src/SCP-firmware:
diff --git a/config/common.config b/config/common.config index a99008c..032e3ea 100644 --- a/config/common.config +++ b/config/common.config @@ -23,9 +23,9 @@ CMAKE=${TOOLS_DIR}/cmake-3.22.4-linux-x86_64/bin/cmake SCP_OUTDIR=$OUTPUT_DIR/tmp_build/scp/ SCP_SRC=$SRC_DIR/SCP-firmware SCP_LOG_LEVEL="INFO" -SCP_BUILD_RELEASE=1 +SCP_BUILD_RELEASE=0 SCP_COMPILER=$ARM_BARE_METAL/arm-none-eabi -SCP_BUILD_MODE="release" +SCP_BUILD_MODE="debug" SCP_PLATFORM_VARIANT_STD=0 SCP_PLATFORM_VARIANT_EXPERIMENT=1 SCP_PLATFORM_VARIANT_MPMM=2
diff --git a/framework/src/fwk_dlist.c b/framework/src/fwk_dlist.c index 6fcfd08b..fa3b3ac7 100644 --- a/framework/src/fwk_dlist.c +++ b/framework/src/fwk_dlist.c @@ -73,10 +73,6 @@ void __fwk_dlist_remove( fwk_assert(node->prev != NULL); fwk_assert(node->next != NULL); - assert(__fwk_slist_contains( - (struct fwk_slist *)list, - (struct fwk_slist_node *)node)); - node->prev->next = node->next; node->next->prev = node->prev; diff --git a/framework/src/fwk_slist.c b/framework/src/fwk_slist.c index b4f41006..a9d09d57 100644 --- a/framework/src/fwk_slist.c +++ b/framework/src/fwk_slist.c @@ -108,8 +108,6 @@ struct fwk_slist_node *__fwk_slist_next( fwk_assert(list != NULL); fwk_assert(node != NULL); - fwk_assert(__fwk_slist_contains(list, node)); - return (node->next == (struct fwk_slist_node *)list) ? NULL : node->next; }
You must recompile the SCP firmware image. The commands to recompile the image are different for Android and the Build Root file system:
export PLATFORM=tc2 export TC_GPU=hwr-prebuilt export TC_TARGET_FLAVOR=fvp export FILESYSTEM=android-fvp ./build-scripts/build-scp.sh clean ./build-scripts/build-scp.sh build ./build-scripts/build-scp.sh deploy build-scripts/build-tfa-trusty.sh build build-scripts/build-tfa-trusty.sh deploy #signed BL1 and SCP_BL1 build-scripts/build-rss.sh deploy #update the fip image build-scripts/build-flash-image.sh deploy
export PLATFORM=tc2 export TC_TARGET_FLAVOR=fvp export FILESYSTEM=buildroot ./build-scripts/build-scp.sh clean ./build-scripts/build-scp.sh build ./build-scripts/build-scp.sh deploy build-scripts/build-tfa.sh build build-scripts/build-tfa.sh deploy #signed BL1 and SCP_BL1 build-scripts/build-rss.sh deploy #update the fip image build-scripts/build-flash-image.sh deploy
The symbol table files corresponding to different firmware are as follows:SCP BL1 Firmware:
output/buildroot/tmp_build/scp/scp/bin/tc2-bl1.elf
output/buildroot/tmp_build/scp/scp/bin/tc2-bl2.elf
Step 3: In the Debugger tab of the SCP debug configuration, include corresponding commands in Execute Debugger Commands to add symbol tables, as shown in the following figure. Each time the debugging connection starts, these commands are automatically executed to load the symbol table files.
Step 4: Click the Debug button to enter the following debugging interface, and you can start debugging.
SCP firmware is divided into three layers, the following figure shows an overview of the components of the SCP firmware:
A module is a unit of code that performs a well-defined operation, or set of operations. Each module might contain elements, which can contain sub-elements. Modules are initialized and driven by the framework through the implementation of the framework module interface.
The framework layer is primarily responsible for initializing memory and interrupts, and managing the modules. This layer also invokes APIs provided by the modules to finish respective tasks. These APIs are defined by the framework and implemented within the modules.
This layer contains CPU architecture-specific code, including CPU booting code and interrupt processing. The module layer must leverage the frameworks layer to access its functionalities and cannot directly invoke this layer's functions.
The Cortex Microcontroller Software Interface Standard (CMSIS) provides a standardized interface for system initialization and low-level hardware access. It enables consistent and efficient software development across different Cortex-M processors. CMSIS RTX2 plays a real-time operating system (RTOS) for SCP firmware.
SCP Firmware includes the following firmwares: