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The System Control Processor (SCP) is a dedicated processor that is used to abstract power and system management tasks away from Application Processors (APs). The SCP Firmware provides a software reference implementation for the SCP on the Arm Total Compute Platform.
The primary services of the SCP firmware include:
Using the Power Policy Unit (PPU), it manages power domain modes in accordance with the constraints of System Control and Management Interface (SCMI) commands that request changes in core, cluster, device, and SoC power states.
Responds to SCMI commands, and manages clock and voltage supplies.
The SCP is responsible for configuring the system to allow the Application processor to boot.
Respond to system events, such as GIC wake requests, local timer events, always-on domain wake requests, debug power requests, and watchdog expiration.
On the Total Compute platform, the SCP firmware consists of ROM firmware (SCP BL1) and RAM firmware (SCP BL2). The SCP BL1 firmware is responsible for configuring the entire system and subsequently powering up the main CPU core of the AP. The SCP BL2 firmware serves as the runtime firmware for the SCP, implementing the main features and functionalities of the SCP.
This guide describes:
This guide assumes that you already set up the debugging environment as described in the Guide to Set Up Debugging Environment for Total Compute Software Stack.
The guidance given in this guide is based on the Total Compute TC2-2023.10.04 code.Note: Future code updates might introduce changes, so the guidance might not apply to all cases.
This guide includes the following sections: