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RE: What is the relationship between Vela versions and Ethos‑U software versions? 1 month ago
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RE: From Free Bird to Jailbird: The Physical Shackle for Agentic AI. Hardware-enforced AI confinement via ARMv9-A CCA. 16 days ago
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RE: Information on the FVP Pointer Authentication crypto algorithm 24 days ago
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RE: MCU STM32 Clock System 20 days ago
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This forum is now read-only. Learn more here. over 1 year ago
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RE: How to create a blog on community.arm.com? over 1 year ago
Compilers and Libraries forum

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RE: Arm Compiler for Embedded 6.19: sizeof(array) does not match actual stack storage when the element type is an aligned typedef — silent buffer overrun 16 days ago
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RE: IAR-workbench error over 1 year ago
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RE: How to apply interleaved batch permutation? 2 months ago
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Best practices for managing firmware OTA updates across a fleet of Arm-based edge gateways at scale? 24 days ago
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RE: I would like to ask for your advice regarding the correct HEX file format. The application scenario is as follows: The customer has a batch of smart card chips that have already been programmed with code. These chips are based on the 8051 platform 18 days ago
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Arm on NAS 5 months ago
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RE: [Mali-G925 / driver 49.1.0] SIGSEGV in libGLES_mali.so on every CPU-side Vulkan sync API (vkWaitForFences, vkWaitSemaphores, vkGetSemaphoreCounterValue, vkQueueWaitIdle) after compute swapchain submit 6 days ago
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Morello is a research program led by Arm which could radically change the way we design and program processors in future, to enable better built-in security.

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RE: Is the power supply universal? 1 month ago
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UEFI variables from UEFI shell 11 months ago

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silent Install of ARM MDK uVision 0

MDK523 0

What is NSC? +1

Is the IDAU also run-time programmable? +1

With regard to slide 38 that talks about calling from secure code to non-secure code, can we assume that the registers pushed {r4-r11} cannot be viewed by examining the stack? +1

Will a BLXNS into a location which is marked as secure, end up in the non-secure state, or will there be an exception? +1

ARM Processor board and Programming +1

Cortex M0+ what means "optionally shifted" at some instructions like EOR (register) +1

Is it possible to set a memory region from non-secure to secure at runtime? +1

Does a library exist for Python to use the secure features of ARMv8-M or can they only be accessed using ASM or C/C++? +1

At what point in time is the boot security map fixed into the chip? +1

What sort of visibility does a non-secure debugger have of the secure sections? +1

Can secure accesses access both secure and nonsecure address map, whereas, nonsecure only access nonsecure part of the address map. +1

configue sd card 0

Who can help me make a decision ? 0