Cortex M0+ what means "optionally shifted" at some instructions like EOR (register)

I have to port some assembler code of a Cortex M4 to a Cortex M0+.

At the Cortex M4 this was used:

EOR      R3,R3,R6,LSL #16

For the M0+ the arm architetcure reference v6m in chapter A6.7.23 says for the EOR:

Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register

But at the description of the encoding this was written:

d = UInt(Rdn);  n = UInt(Rdn);  m = UInt(Rm);  setflags = !InITBlock();
(shift_t, shift_n) = (SRType_LSL, 0);

Which was interpreted from me as there was no optionally-shift. Because shift_n was declared as 0.

But in the pseudo-code-part "Operation" this was written:

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
    result = R[n] EOR shifted;
    R[d] = result;
    if setflags then
        APSR.N = result<31>;
        APSR.Z = IsZeroBit(result);
        APSR.C = carry;
        // APSR.V unchanged

That seems as that a shift was supported.

I didn`t found a syntax which was accepted from my compiler. So my question was, ist the "optionally-shift" only a mistake in writing or has the EOR the possibility to shift?

Best regards

Volker