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Forums

  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 8 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    713 questions
    Colin Campbell
    RE: AHB: Address and control signal stable during waited write access 13 days ago Arm Employee Badge
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 7 months ago Arm Employee Badge
  • TOSA forum

    Tensor Operator Set Architecture (TOSA) provides a set of whole-tensor operations commonly employed by Deep Neural Networks.
    1 question
    Oliver Beirne
    RE: Forum FAQs 2 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 10 years ago Arm Employee Badge
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All questions in this Community
  • Answered

    no TRACE available when debugger is an CMSIS-DAP Debugger (MCU link) +1

    2413 views
    4 replies
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Startup files for MK10DN128xxx5 NXP MCUs 0

    849 views
    1 reply
    Latest over 1 year ago
    by Stephen Theobald Arm Employee Badge
  • Not Answered

    Lora SX1278 with STM32F1C308 is not running (using KeilC u5 and Standard Peripheral Library). I can't write and read command to Lora register. Please someone help me. 0

    854 views
    1 reply
    Latest over 1 year ago
    by Annie
  • Not Answered

    Relationship between ARM's shareability domain, cache maintenance and barrier 0

    • Cache coherency
    • Armv8-A
    • barrier
    • memory-model
    • Cache Architecture
    • Memory Management
    1852 views
    2 replies
    Latest over 1 year ago
    by Joon Kang
  • Answered

    Return from MemManageFault +1

    • mpu
    • MemManageFault
    • Cortex-M4
    2006 views
    3 replies
    Latest over 1 year ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    FVP_corstone-1000 fast models are empty 0

    • corstone-1000
    • Fast Models
    • Fixed Virtual Platforms (FVPs)
    • fvp
    579 views
    0 replies
    Started over 1 year ago
    by Emrehan Karaoglu
  • Answered

    Multiple BSD connections 0

    • BSD Networking
    3838 views
    8 replies
    Latest over 1 year ago
    by Franc Urbanc Arm Employee Badge
  • Suggested Answer

    Problem with ARM DS IDE 0

    3323 views
    6 replies
    Latest over 1 year ago
    by neha sharma
  • Answered

    Support for Huge Pages in SMMU 0

    • SMMUv3
    2619 views
    4 replies
    Latest over 1 year ago
    by Jonathan Kang
  • Not Answered

    Exploring SIMD and Java Vector API Performance: Benchmarking Across Multiple Machines 0

    • benchmark
    • High Performance Computing (HPC)
    • java
    • Arm
    • jmh
    • SIMD and Vector Processing Instructions
    • maven
    • SIMD and Vector Execution
    1776 views
    0 replies
    Started over 1 year ago
    by Ioannis Polyzos
  • Suggested Answer

    In AXI-5, can BVALID be asserted on same cycle as WLAST? 0

    • AMBA 4
    • AXI5
    • AXI4
    • AMBA 5
    1552 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    related to AXI4 0

    1379 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Help me fix this please +1

    2848 views
    2 replies
    Latest over 1 year ago
    by Minh Nguyen
  • Not Answered

    C8051F580 uVision 5 compiler: ?C_STARTUP where is this value defined? 0

    472 views
    0 replies
    Started over 1 year ago
    by Fausto Bartra
  • Answered

    Memory Frequencies per Core 0

    • Memory Management Unit (MMU)
    • Cortex-A
    • x1
    1647 views
    2 replies
    Latest over 1 year ago
    by FabianSchuetze
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