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Forums

  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 7 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    709 questions
    Toshihisa Oishi
    RE: How to enable lumex FVP cache_state_model ? It seems slc cache could not be modelld? 3 hours ago Arm Employee Badge
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 6 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 10 years ago Arm Employee Badge
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All questions in this Community
  • Not Answered

    Will an outer non-cachable-write invalidate cacheline when hit in l2cache, with shared override bit set 0

    777 views
    0 replies
    Started over 2 years ago
    by shch
  • Not Answered

    Coremark value for the Cortex A78-AE processor? 0

    1518 views
    0 replies
    Started over 2 years ago
    by BalaS
  • Answered

    Linux SGI's on quad Cortex-A53 0

    4406 views
    3 replies
    Latest over 2 years ago
    by andreas2025
  • Answered

    Cortex M3 goes into osRtxIdleThread when jumping to __main 0

    • Cortex-M3
    • Cortex-M
    1394 views
    2 replies
    Latest over 2 years ago
    by Arran
  • Answered

    Armv8-2 Error Injection Registers 0

    • Armv8-A
    1939 views
    3 replies
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    FVP peripheral supports 0

    • SMMUv3
    • Fixed Virtual Platforms (FVPs)
    1286 views
    1 reply
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    When GICD_IERRR bit set ? 0

    • GICv3/v4
    • CoreLink GIC-600 Generic Interrupt Controller
    • CoreLink GIC-600AE
    1661 views
    3 replies
    Latest over 2 years ago
    by Namu
  • Suggested Answer

    Is SGI send when redistributor is power down? 0

    • GICv3/v4
    • Generic Interupt Controller
    1923 views
    1 reply
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    About CPU behavior when it receives error response signal during reading or writing 0

    1625 views
    2 replies
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    send integer through Bluetooth from TM4C123 microcontroller 0

    986 views
    2 replies
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    Processing units and Fragment Warps in G78 and Immortalis-G715 +1

    3263 views
    3 replies
    Latest over 2 years ago
    by Peter Harris Arm Employee Badge
  • Not Answered

    Understanding ARM core performance 0

    1284 views
    0 replies
    Started over 2 years ago
    by BalaS
  • Not Answered

    Understanding ARM core performance 0

    606 views
    0 replies
    Started over 2 years ago
    by BalaS
  • Suggested Answer

    how to perf the kernel in arm mobile studio by streamline ? 0

    • arm streamline
    3689 views
    4 replies
    Latest over 2 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Question about speeding up PSO pre-warm 0

    • vulkan
    • Compilers
    3214 views
    2 replies
    Latest over 2 years ago
    by Oliver Beirne Arm Employee Badge
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