Hi, I use NIC400 bus.
And I have quesetion about reset sequence when I use more than 2 clock domain.
- X Slave interface is ACLK. (AXI3)
- Y Slave interface is BCLK. (AXI3)
- P Master interface is ACLK (AXI3)
- Q Master interface is BCLK (AXI3)
- Connected X - P, X - Q, Y - P, Y - Q
X - P and Y - Q didn't make problem (same domain)
but if I assert ARESETn -> assert BRESETn for Y - P connection, there are make some issue.
1. Becaouse of ARESETn assert, "X - Q"'s async fifo's write pointer set 0.
and it make read pointer increase.
So, unexpected values are transfer for Q master interface. (untill BRESETn assert)
2. Because of AXI3 interface use 5 channels, read channel transfer unexpected value (assert didn't requested rvalid).
Valid signal of AW, AR, W channels are transfer Y (BCLK) to P (ACLK), so async fifo read pointer is not increased (because of reset).
Valid signal of But R, B channels are transfer P (ACLK) to Y (BCLK), so async fifo read pointer is increased (untill BRESETn assert)
So. I want to know reset sequence of AXI bus (used multi domain)
(I have solution with disable clock for don't compare read/write pointer. But I want to know other solution)