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Cortex-R / R-Profile forum
Description
Cortex-R series processors deliver fast and deterministic processing and high performance, while meeting real-time constraints. Cortex-R52, Cortex-R8, Cortex-R7, Cortex-R5, Cortex-R4.
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62 Questions
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Unanswered questions
Regarding the J bit
Answered
12 days ago
What is the priority between synchronous data abort and FIQ in Cortex-R5F?
Answered
22 days ago
Cortex-R5: Divide-by-zero
Not Answered
1 month ago
Cortex R8 axi unaligned transfer
Suggested Answer
1 month ago
Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA?
Not Answered
2 months ago
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Answered
Regarding the J bit
0
461
views
4
replies
Latest
6 days ago
by
42Bastian Schick
Answered
What is the priority between synchronous data abort and FIQ in Cortex-R5F?
0
Cortex-R5
Interrupt
1038
views
6
replies
Latest
19 days ago
by
Etienne Alepins
Not Answered
Cortex-R5: Divide-by-zero
0
Armv7 Exception Model
Cortex-R5
Processors
Software Development
1191
views
6
replies
Latest
1 month ago
by
Tau
Suggested Answer
Cortex R8 axi unaligned transfer
0
program
cortex-r8
735
views
2
replies
Latest
1 month ago
by
Ben Chen
Not Answered
Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA?
0
1178
views
4
replies
Latest
1 month ago
by
RLA
Not Answered
R52 Development Boards
0
Cortex-R52
Development Boards
Software Development
264
views
0
replies
Started
1 month ago
by
Poz1
Not Answered
Memory Protection Unit - Complexity in usage
0
1437
views
7
replies
Latest
2 months ago
by
Andy Neil
Not Answered
TrustZone in CortexR
0
Cortex-R
virtualization
TrustZone
979
views
3
replies
Latest
2 months ago
by
42Bastian Schick
Answered
Debug Unit Cortex - R
0
925
views
3
replies
Latest
2 months ago
by
Martin Weidmann
Not Answered
Is CPSR.F settable through debug port? (e.g. JTAG)
0
Cortex-R5
CPSR
Debugging
772
views
3
replies
Latest
2 months ago
by
42Bastian Schick
Not Answered
Instruction Fault Generation
0
628
views
2
replies
Latest
2 months ago
by
techguyz
Not Answered
Inner/Outer Cacheability in Cortex V8-R
0
915
views
3
replies
Latest
2 months ago
by
David Harriman-Smith
Not Answered
Memory barrier when accessing strongly ordered memory
0
861
views
3
replies
Latest
2 months ago
by
Martin Weidmann
Not Answered
ARM assembly instruction for writing Zero to SPSR
0
597
views
1
reply
Latest
2 months ago
by
42Bastian Schick
Not Answered
Inner/Outer share ability in Cortex R52
0
241
views
0
replies
Started
2 months ago
by
Reco
Not Answered
TCM arbitration hazard: Considerations for Firmware
0
Cortex-R
Cortex-R5
318
views
0
replies
Started
3 months ago
by
c0deface
Answered
Cortex R5 behavior when a masked imprecise/asynchronous abort occurs
+1
3378
views
6
replies
Latest
3 months ago
by
Martin Weidmann
Answered
Data Abort on read, although write can be executed without any abort.
+1
Armv7 Exception Model
Memory
1382
views
3
replies
Latest
4 months ago
by
r4c00n
Not Answered
The Peripherals memory map of FVP_BaseR_Cortex-R52x1
0
Cortex-R52
Fixed Virtual Platforms (FVPs)
PrimeCell UART (PL011)
388
views
0
replies
Started
5 months ago
by
Jex1x
Not Answered
Is it OK to bypass all clock gates in Cortex-R52?
0
Cortex-R52
Clocking Structures & Timing Mechanisms
SoC FPGA
398
views
0
replies
Started
5 months ago
by
Zack Yang
>