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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3656 Questions
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  • Not Answered

    AMBA CHI Issue H Figure B2.47 0

    71 views
    0 replies
    Started 1 day ago
    by Jay Khandkar
  • Not Answered

    Cortex-R52+ and Cortex-M4 FPU name and version 0

    • Floating Point
    • Cortex-M4
    • Cortex-R52+
    70 views
    0 replies
    Started 1 day ago
    by Grace WANG
  • Suggested Answer

    Normal World-Realm World and RME-RMM architecture 0

    427 views
    3 replies
    Latest 3 days ago
    by Lucas Blake
  • Not Answered

    Multiple issues with Saturating Instructions Chapter in all DGUG for Cortex-M 0

    • Cortex-M
    582 views
    0 replies
    Started 11 days ago
    by Jesse Silverman
  • Not Answered

    Agilex 5 AXI Throughput 0

    370 views
    0 replies
    Started 12 days ago
    by Eric Opitz
  • Answered

    ADIv5 CTRL/STAT TRNCNT field width clarification 0

    • SWD
    • Arm Debugger
    272 views
    1 reply
    Latest 17 days ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Exclusive load and stores require enabled caches on real hardware (Raspberry Pi 3b+ - Cortex-A53) 0

    310 views
    1 reply
    Latest 17 days ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    CORTEX R5 TCM ECC ERROR ISR NOT working 0

    622 views
    0 replies
    Started 1 month ago
    by Subbu
  • Suggested Answer

    AMBA CHI: How does an RN System Address Map (SAM) route transactions to a remote die via a C2C bridge? 0

    681 views
    1 reply
    Latest 1 month ago
    by Simone Secchi Arm Employee Badge
  • Answered

    about writing to GIC ICC_AP0Rn and ICC_AP1Rn 0

    • GICv3/v4
    573 views
    1 reply
    Latest 1 month ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    How request node handle snoop transaction before it receives DataSepResp of last transaction in CHI specification? 0

    • AMBA 5 CHI
    473 views
    0 replies
    Started 1 month ago
    by Dong Luo
  • Answered

    GCC support for R52plus+fpuv5-sp-d16 +1

    854 views
    4 replies
    Latest 1 month ago
    by chong wang
  • Suggested Answer

    How to obtain the "Bare metal example" mentioned in the document "Learn the architecture - AArch64 virtualization Guide" 0

    586 views
    1 reply
    Latest 1 month ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Armv7-M architecture reference manual chapter a3 is the title written incorrectly? 0

    • CPU Architecture
    • Armv7-M
    1129 views
    0 replies
    Started 1 month ago
    by Kaze
  • Answered

    How to prevent Non-Secure Unprivileged (nonPriv) code from executing SG instructions to enter TrustZone-M Secure World? 0

    • TrustZone for Armv8-M
    1149 views
    2 replies
    Latest 1 month ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Cortex-M0+: disable all interrupts except N (or >=N priority) without BASEPRI 0

    • Cortex-M0+
    1918 views
    0 replies
    Started 2 months ago
    by Michael Rodriguez
  • Not Answered

    From Free Bird to Jailbird: The Physical Shackle for Agentic AI. Hardware-enforced AI confinement via ARMv9-A CCA. 0

    4478 views
    4 replies
    Latest 3 months ago
    by Alexander Colclough
  • Not Answered

    Cortex-M3/M4 Benchmark Anomaly: Why is Code in Flash faster than Code in SRAM? 0

    1004 views
    0 replies
    Started 3 months ago
    by d d
  • Not Answered

    Cortext-M33 instruction cycle 0

    713 views
    0 replies
    Started 3 months ago
    by Stom
  • Answered

    Figure B2.1 in CHI Spec Issue G 0

    1222 views
    1 reply
    Latest 3 months ago
    by Ben Hicks Arm Employee Badge
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