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Cortex-R / R-Profile forum
Description
Cortex-R series processors deliver fast and deterministic processing and high performance, while meeting real-time constraints. Cortex-R52, Cortex-R8, Cortex-R7, Cortex-R5, Cortex-R4.
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62 Questions
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Unanswered questions
Regarding the J bit
Answered
2 months ago
What is the priority between synchronous data abort and FIQ in Cortex-R5F?
Answered
2 months ago
Cortex-R5: Divide-by-zero
Answered
3 months ago
Cortex R8 axi unaligned transfer
Answered
3 months ago
Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA?
Answered
3 months ago
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Answered
Regarding the J bit
0
1457
views
4
replies
Latest
1 month ago
by
42Bastian Schick
Answered
What is the priority between synchronous data abort and FIQ in Cortex-R5F?
0
Cortex-R5
Interrupt
1824
views
6
replies
Latest
2 months ago
by
Etienne Alepins
Answered
Cortex-R5: Divide-by-zero
+1
Armv7 Exception Model
Cortex-R5
Processors
Software Development
1943
views
6
replies
Latest
2 months ago
by
Tau
Answered
Cortex R8 axi unaligned transfer
0
program
cortex-r8
1181
views
2
replies
Latest
3 months ago
by
Ben Chen
Answered
Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA?
+1
1753
views
4
replies
Latest
3 months ago
by
RLA
Not Answered
R52 Development Boards
+1
Cortex-R52
Development Boards
Software Development
416
views
0
replies
Started
3 months ago
by
Poz1
Answered
Memory Protection Unit - Complexity in usage
+1
2177
views
7
replies
Latest
3 months ago
by
Andy Neil
Answered
TrustZone in CortexR
+1
Cortex-R
virtualization
TrustZone
1459
views
3
replies
Latest
3 months ago
by
42Bastian Schick
Answered
Debug Unit Cortex - R
0
1398
views
3
replies
Latest
4 months ago
by
Martin Weidmann
Answered
Is CPSR.F settable through debug port? (e.g. JTAG)
+1
Cortex-R5
CPSR
Debugging
1213
views
3
replies
Latest
4 months ago
by
42Bastian Schick
Answered
Instruction Fault Generation
+1
1004
views
2
replies
Latest
4 months ago
by
techguyz
Answered
Inner/Outer Cacheability in Cortex V8-R
+1
1366
views
3
replies
Latest
4 months ago
by
David Harriman-Smith
Answered
Memory barrier when accessing strongly ordered memory
+1
1280
views
3
replies
Latest
4 months ago
by
Martin Weidmann
Answered
ARM assembly instruction for writing Zero to SPSR
+1
907
views
1
reply
Latest
4 months ago
by
42Bastian Schick
Not Answered
Inner/Outer share ability in Cortex R52
0
391
views
0
replies
Started
4 months ago
by
Reco
Not Answered
TCM arbitration hazard: Considerations for Firmware
0
Cortex-R
Cortex-R5
458
views
0
replies
Started
5 months ago
by
c0deface
Answered
Cortex R5 behavior when a masked imprecise/asynchronous abort occurs
+1
4074
views
6
replies
Latest
5 months ago
by
Martin Weidmann
Answered
Data Abort on read, although write can be executed without any abort.
+1
Armv7 Exception Model
Memory
1858
views
3
replies
Latest
6 months ago
by
r4c00n
Not Answered
The Peripherals memory map of FVP_BaseR_Cortex-R52x1
0
Cortex-R52
Fixed Virtual Platforms (FVPs)
PrimeCell UART (PL011)
528
views
0
replies
Started
6 months ago
by
Jex1x
Not Answered
Is it OK to bypass all clock gates in Cortex-R52?
0
Cortex-R52
Clocking Structures & Timing Mechanisms
SoC FPGA
543
views
0
replies
Started
7 months ago
by
Zack Yang
>