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Cortex-R / R-Profile forum
Description
Cortex-R series processors deliver fast and deterministic processing and high performance, while meeting real-time constraints. Cortex-R52, Cortex-R8, Cortex-R7, Cortex-R5, Cortex-R4.
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57 Questions
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Unanswered questions
Memory Protection Unit - Complexity in usage
Not Answered
5 days ago
TrustZone in CortexR
Not Answered
2 days ago
Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA?
Not Answered
3 days ago
Debug Unit Cortex - R
Answered
8 days ago
Is CPSR.F settable through debug port? (e.g. JTAG)
Not Answered
8 days ago
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Not Answered
Memory Protection Unit - Complexity in usage
0
340
views
5
replies
Latest
16 hours ago
by
42Bastian Schick
Not Answered
TrustZone in CortexR
0
Cortex-R
virtualization
TrustZone
395
views
3
replies
Latest
2 days ago
by
42Bastian Schick
Not Answered
Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA?
0
141
views
1
reply
Latest
3 days ago
by
Peter Rielly
Answered
Debug Unit Cortex - R
0
343
views
3
replies
Latest
5 days ago
by
Martin Weidmann
Not Answered
Is CPSR.F settable through debug port? (e.g. JTAG)
0
Cortex-R5
CPSR
Debugging
305
views
3
replies
Latest
7 days ago
by
42Bastian Schick
Not Answered
Instruction Fault Generation
0
241
views
2
replies
Latest
8 days ago
by
techguyz
Not Answered
Inner/Outer Cacheability in Cortex V8-R
0
459
views
3
replies
Latest
17 days ago
by
David Harriman-Smith
Not Answered
Memory barrier when accessing strongly ordered memory
0
382
views
3
replies
Latest
21 days ago
by
Martin Weidmann
Not Answered
ARM assembly instruction for writing Zero to SPSR
0
223
views
1
reply
Latest
21 days ago
by
42Bastian Schick
Not Answered
Inner/Outer share ability in Cortex R52
0
61
views
0
replies
Started
21 days ago
by
Reco
Not Answered
TCM arbitration hazard: Considerations for Firmware
0
Cortex-R
Cortex-R5
151
views
0
replies
Started
1 month ago
by
c0deface
Answered
Cortex R5 behavior when a masked imprecise/asynchronous abort occurs
+1
2634
views
6
replies
Latest
1 month ago
by
Martin Weidmann
Answered
Data Abort on read, although write can be executed without any abort.
+1
Armv7 Exception Model
Memory
845
views
3
replies
Latest
2 months ago
by
r4c00n
Not Answered
The Peripherals memory map of FVP_BaseR_Cortex-R52x1
0
Cortex-R52
Fixed Virtual Platforms (FVPs)
PrimeCell UART (PL011)
222
views
0
replies
Started
2 months ago
by
Jex1x
Not Answered
Is it OK to bypass all clock gates in Cortex-R52?
0
Cortex-R52
Clocking Structures & Timing Mechanisms
SoC FPGA
226
views
0
replies
Started
3 months ago
by
Zack Yang
Not Answered
reference source code to verify the Cortex-R52
0
Cortex-R52
Evaluation Boards
508
views
1
reply
Latest
3 months ago
by
Jorney
Answered
ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence
0
Cortex-A53
Cortex-R
CoreLink CCI-400 Cache Coherent Interconnect
Cache coherency
Cortex-R5
Cortex-A
1470
views
6
replies
Latest
4 months ago
by
Sandeep Bobba
Not Answered
PMU Register description is not clear in Arm Cortex -R52 Processor Revision: r1p1
0
Cortex-R52
Cortex-R
api
368
views
0
replies
Started
7 months ago
by
Reco
Not Answered
Cache ECC in Cortex-R5 & Event bus
+1
Cortex-R
Cortex-R5
Cache
1123
views
2
replies
Latest
9 months ago
by
Johnson Berry
Not Answered
When is Cortex-R5 Virtual Peripheral AXI bus used?
0
Cortex-R
AXI
Cortex-R5
491
views
0
replies
Started
10 months ago
by
Etienne Alepins
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