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Cortex-R / R-Profile forum
Description
Cortex-R series processors deliver fast and deterministic processing and high performance, while meeting real-time constraints. Cortex-R52, Cortex-R8, Cortex-R7, Cortex-R5, Cortex-R4.
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23 Questions
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Unanswered questions
Data Abort on read, although write can be executed without any abort.
Answered
19 days ago
The Peripherals memory map of FVP_BaseR_Cortex-R52x1
Not Answered
28 days ago
Is it OK to bypass all clock gates in Cortex-R52?
Not Answered
1 month ago
reference source code to verify the Cortex-R52
Not Answered
1 month ago
ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence
Answered
3 months ago
Related Tags
armv7-r
C
cache
cortex-r
cortex-r4
Cortex-R5
cortex-r52
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Cortex-R / R-Profile forum
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Answered
Data Abort on read, although write can be executed without any abort.
+1
420
views
3
replies
Latest
19 days ago
by
r4c00n
Not Answered
The Peripherals memory map of FVP_BaseR_Cortex-R52x1
0
142
views
0
replies
Started
28 days ago
by
Jex1x
Not Answered
Is it OK to bypass all clock gates in Cortex-R52?
0
134
views
0
replies
Started
1 month ago
by
Zack Yang
Not Answered
reference source code to verify the Cortex-R52
0
327
views
1
reply
Latest
1 month ago
by
Jorney
Answered
ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence
0
1048
views
6
replies
Latest
2 months ago
by
Sandeep Bobba
Not Answered
PMU Register description is not clear in Arm Cortex -R52 Processor Revision: r1p1
0
276
views
0
replies
Started
5 months ago
by
Reco
Not Answered
Cache ECC in Cortex-R5 & Event bus
+1
915
views
2
replies
Latest
7 months ago
by
Johnson Berry
Not Answered
When is Cortex-R5 Virtual Peripheral AXI bus used?
0
410
views
0
replies
Started
8 months ago
by
Etienne Alepins
Answered
Is Advanced-SIMD supported in Cortex-R5F?
0
1280
views
3
replies
Latest
8 months ago
by
Joseph Yiu
Not Answered
Hypervisor Mode to System Mode in R52 cortex
0
519
views
0
replies
Started
8 months ago
by
Himanshu Khanna
Not Answered
Porting FreeRTOS On R-52 Cortex
0
947
views
1
reply
Latest
8 months ago
by
Georgia James
Not Answered
Can we inspect contents of the return stack to get the call tree?
0
995
views
2
replies
Latest
8 months ago
by
Etienne Alepins
Not Answered
Does Cortex R4x support SPI?
0
395
views
0
replies
Started
10 months ago
by
Anurag_Kumar
Answered
Cortex-R5: Data abort handling
0
2043
views
5
replies
Latest
11 months ago
by
42Bastian Schick
Suggested Answer
Disabling PFU / instruction pre-fetch on Cortex-R4?
0
1541
views
4
replies
Latest
over 1 year ago
by
Martin Weidmann
Not Answered
ARMv7-R intrinsics?
0
815
views
1
reply
Latest
over 1 year ago
by
Ryan Thomas
Not Answered
Right way to jump to New Vector Table without Reset
0
845
views
0
replies
Started
over 1 year ago
by
ZXCFD
Not Answered
Very Urgent :VIC in ARM Cortex R4
0
2354
views
8
replies
Latest
over 1 year ago
by
Joseph Yiu
Suggested Answer
Bit scan Instruction ARM cortex R4
0
1400
views
1
reply
Latest
over 1 year ago
by
Joseph Yiu
Not Answered
Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?
0
1466
views
4
replies
Latest
over 1 year ago
by
AJ
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