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Cortex-R / R-Profile forum
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Cortex-R / R-Profile forum
Description
Cortex-R series processors deliver fast and deterministic processing and high performance, while meeting real-time constraints. Cortex-R52, Cortex-R8, Cortex-R7, Cortex-R5, Cortex-R4.
Threads
91 Questions
Tell us what you think
Unanswered questions
Forum FAQs
8 months ago
Memory Alignment for VSTM/VLDM Instructions on Cortex R52
Not Answered
6 days ago
Unsupported exclusive Data Abort
Not Answered
1 month ago
can the Cortex-R5 processor support Cross Trigger Interface (CTI)?
Not Answered
1 month ago
Inner/Outer Cacheability in Cortex V8-R
Answered
over 2 years ago
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Forum FAQs
0
ARM Community
1037
views
0
replies
Started
8 months ago
by
Annie
Not Answered
Memory Alignment for VSTM/VLDM Instructions on Cortex R52
0
Cortex-R52
Arm Assembly Language (ASM)
105
views
1
reply
Latest
5 days ago
by
42Bastian Schick
Not Answered
Unsupported exclusive Data Abort
0
296
views
0
replies
Started
1 month ago
by
XNoOp
Not Answered
can the Cortex-R5 processor support Cross Trigger Interface (CTI)?
0
144
views
0
replies
Started
1 month ago
by
chenyu
Answered
Inner/Outer Cacheability in Cortex V8-R
+1
5072
views
4
replies
Latest
1 month ago
by
XNoOp
Not Answered
how to connect the ACP (accelerate coherence port) interface with my SoC system
0
167
views
0
replies
Started
1 month ago
by
chenyu
Not Answered
is there CPS instruction alternatives to jump from EL1 to EL0 at boot time?
0
Cortex-R52
1058
views
7
replies
Latest
1 month ago
by
42Bastian Schick
Not Answered
R52 , priority level = 31 : what is the expected behavior?
0
Cortex-R52
Interrupt Handling
Generic Interrupt Controller
165
views
0
replies
Started
1 month ago
by
kduplantier
Answered
TCM interface timing of Arm Cortex-r4f
0
1405
views
11
replies
Latest
1 month ago
by
Aaliyah
Not Answered
how to use TCM interface of Arm Cortex-r4f
0
399
views
2
replies
Latest
1 month ago
by
Aaliyah
Answered
Cortex-R4 PMU CP15 cycle counter value : runto readout vs step by step to readout..
0
661
views
4
replies
Latest
1 month ago
by
d.ry
Suggested Answer
CMSIS-RTOS2 not working on the F103RB board
0
494
views
1
reply
Latest
2 months ago
by
Andy Neil
Not Answered
Longer pipelines on Cortex R's vs real-time & performance
0
1290
views
7
replies
Latest
3 months ago
by
42Bastian Schick
Not Answered
Why there is no layer like CMSIS for Cortex R ?
0
720
views
3
replies
Latest
3 months ago
by
42Bastian Schick
Suggested Answer
How to get/download core_cr5.h
0
Cortex-R5
2086
views
3
replies
Latest
3 months ago
by
d.ry
Answered
ATCM ECC error causes prefetch abort despite ECC check being disabled.
0
Armv7 Exception Model
Cortex-R4
4035
views
4
replies
Latest
3 months ago
by
Alex21
Answered
Application note on R4 and R5 differences
+1
Cortex-R
Cortex-R5
Cortex-R4
7037
views
7
replies
Latest
3 months ago
by
EllieC
Not Answered
Is there primask core register in cortex-R5
0
2484
views
2
replies
Latest
3 months ago
by
EllieC
Not Answered
Multiple registers in CPU
0
2372
views
0
replies
Started
4 months ago
by
techguyz
Answered
Is Advanced-SIMD supported in Cortex-R5F?
0
Cortex-R
Cortex-R5
Armv7-R
SIMD and Vector Execution
7144
views
5
replies
Latest
5 months ago
by
Zenon Xiu (修志龙）
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