Dear ARM support,
We are currently developing a product based on the Agilex 5 which is based on A76 and A55 cores. We are facing the problem that the throughput via the HPS-to-FPGA (H2F) and Light Weight HPS-to-FPGA (LWH2F) bridges is significantly lower than we expect. We have asked Altera for support but so far haven't received an explanation. Since the CPU and many other components in the SoC were developed by ARM we are wondering if you recognize this problem.
You can find the original support ticket here: community.altera.com/.../354956
I will briefly summarize the problem, so as to not repeat too much information:- We've upgraded from Cyclone 5 to Agilex 5. We've noticed that writing via LWH2F bridge is significantly slower. - We're writing data from a kernel driver by dereferencing a pointer (e.g. for (int i=0; i<10000; i++){*ptr = i}). This can obviously be improved by using memcpy, mapping the memory using ioremap_wc(), and using the wider H2F bridge. But still, the throughput is way below the theoretical maximum.- When observing the AXI bus with an oscilloscope we observe three issues: - The write requests are not pipelined. - The latency between subsequent write requests is high. After a write is done (bvalid) it still takes ~200ns until the next request is issued (awvalid). - The burst size is smaller than expected. On the H2F interface we see bursts of size 4 while theoretically a burst size of 8 should be possible.
Kind Regards,Eric Opitz