ADIv5 CTRL/STAT TRNCNT field width clarification

Hi,

I have a question regarding the TRNCNT field in the DP CTRL/STAT register in the ARM Debug Interface v5 Architecture Specification.

In Figure 6-3 (Control/Status Register bit assignments), TRNCNT is shown as [23:12]. The Transaction Counter section also explicitly states that the TRNCNT field is [23:12].

However, the CTRL/STAT register table lists TRNCNT as [21:12].

Could you please confirm which bit range is correct for TRNCNT: [23:12] or [21:12]?

Thanks.