The CHI.E spec says that we need to consider both protocol and link to be inactive for the entry to higher level clock gating and low power optimisation. However, it also says that "SACTIVE signaling is orthogonal to the LINKACTIVE states". So say we are a subordinate block want to move to higher level clock gating or low power mode. We can initiate deactivation of the link from our end and get link deactivated. But what about the incoming RXSACTIVE from the other side. If SACTIVE is orthogonal to LINKACTIVE, does it mean that we are on the mercy of the other side to pull RXSACTIVE low for us to be able to move to higher level clock gating or low power mode? What if some implementation on the other side tied off its TXSACTIVE to 0?
Or is there some spec guarantee that RXSACTIVE needs to deassert in a timely manner if the other side deactivated the link?
Can someone please help clarify the expected behaviour for this scenario?
Thanks!