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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3656 Questions
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  • Answered

    Realtime differences between Cortex-R and M and Hardware Features 0

    • Cortex-R52
    • Architecture
    • Cortex-R
    • Cortex-M7
    • Cortex-R5
    • Real-Time
    • Cortex-M
    • Cortex-M33
    2182 views
    2 replies
    Latest 3 months ago
    by 42Bastian Schick
  • Suggested Answer

    Bit Trimming - A New Approach For The Optimization of Thumb 32-Bit x 32-Bit --> (top) 32-bit Calculations 0

    • Cortex-M0
    • Cortex-M0+
    2786 views
    4 replies
    Latest 3 months ago
    by 42Bastian Schick
  • Not Answered

    How can I develop a hybrid kernel? 0

    781 views
    0 replies
    Started 3 months ago
    by saulo carrillo
  • Not Answered

    Potential Issue in ARM7TDMI Documentation 0

    • Arm7tdmi
    • Documentation
    1324 views
    1 reply
    Latest 4 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    AMBA CHI bus atomics + ARM core implementation for big-endian 0

    902 views
    0 replies
    Started 4 months ago
    by Shane Lardinois
  • Suggested Answer

    Question about CHI spec:Issue about the Relationship Between TxnID and ReturnTxnID for HN DMT=0 ReadNoSnp Transaction 0

    1477 views
    1 reply
    Latest 4 months ago
    by Cecilia Cheng Arm Employee Badge
  • Suggested Answer

    Synchronous FPU Exception in Cortex R5 0

    • Cortex-R5
    1361 views
    1 reply
    Latest 4 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    ​[UPDATE] Guardian Angæl Protocol (GAP) V1.1 — Billion-Cycle Validation Results 0

    1361 views
    1 reply
    Latest 4 months ago
    by Alexander Colclough
  • Not Answered

    MBIST test L1 and L2 cache 0

    794 views
    0 replies
    Started 4 months ago
    by Ping L_0941
  • Not Answered

    Processor has escalated a configurable-priority exception to HardFault 0

    980 views
    0 replies
    Started 5 months ago
    by Aakash Tegginamani
  • Not Answered

    ECC Test for A53 Cache memories 0

    • Cortex-A53
    • Cache Architecture
    900 views
    0 replies
    Started 5 months ago
    by Nihar Potturu
  • Not Answered

    CFP RCTX instruction on Neoverse-N3 0

    • EL1
    • AArch64
    • Security
    • Neoverse
    • Branch Prediction
    835 views
    0 replies
    Started 5 months ago
    by Gal Kaptsenel
  • Answered

    Cortex-M85 & Cortex-M55 Core ID 0

    • Cortex-M55
    • Cortex-M85
    2880 views
    3 replies
    Latest 5 months ago
    by Mahmood Yakub Arm Employee Badge
  • Suggested Answer

    AXI5 0

    • AMBA 5
    1616 views
    2 replies
    Latest 5 months ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    Dormant state for debug 0

    • Debugging
    635 views
    0 replies
    Started 5 months ago
    by Yael Kanter-Weisman
  • Not Answered

    the issue of different execution times for the same assembly code on Cortex-A53 0

    1613 views
    4 replies
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Question about Snoop Response for SnpCleanShared using CHIE.b? 0

    • CHI
    683 views
    1 reply
    Latest 6 months ago
    by Ben Hicks Arm Employee Badge
  • Suggested Answer

    Does TCM configured as Strongly ordered memory have alignment alignment requirements? 0

    • Cortex-R5
    937 views
    3 replies
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How AXI Handle unaligned transfer in FIX and INCR mode. 0

    1151 views
    2 replies
    Latest 6 months ago
    by roshan ekre
  • Not Answered

    M33 parallel trace clock 0

    • Debug and Trace
    553 views
    0 replies
    Started 6 months ago
    by Yael Kanter-Weisman
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