The next generation of ARM Cortex-M processors will be powered by a new architecture version called ARMv8-M architecture. This document provides a technical overview of various enhancements in the new architecture, as well as an introduction to the security technology, called TrustZone for ARMv8-M. This document also introduces AMBA 5 AHB5 which enables security management at a system level, and covers various use cases of the new technology.
Introduction to the ARMv8‑M Architecture
TrustZone technology for ARMv8‑M Architecture
ARM C Language Extension (ACLE)
ACLE Extensions for ARMv8‑M
Secure software guidelines for ARMv8‑M based platforms
System Design for ARMv8-M
Exceptions and Interrupts
ARMv8‑M Exception Handling
Fault Handling and Detection
Power management and sleep modes
ARMv8-M processor power management secure state protection
ARMv8‑M Processor Debug
Memory Protection Unit for ARMv8‑M based platforms
RTOS design considerations for ARMv8‑M based platforms
ARMv8-M software development with ARM Compiler 6
Chapter 9 : Building Secure and Non-secure Images Using ARMv8-M Security Extensions
TrustZone software development in Keil MDK
Keil Application Note 291: Using TrustZone on ARMv8-M
Security extension details for compiler vendors
ARMv8-M Security Extension: Requirements on Development Tools
ARMv8-M software development
EW2017 - Software Development on ARMv8-M Arhcitecture
mbed(TM)OS deployment on Armv8-M
EW2017 - High-End Security Features for Low-End Microcontrollers
EW2019 - How RTOS should work in a TrustZone for Armv8-M environment
Hello daith ,
thank you for your detailed reply.
I understood your comments as that the FPU lazy stacking was always enabled, and the stacking (if needed) would be done as the normal general registers. Also in the case of change from Secure to Non-Secure world, all the regsisters would be cleared.
Is my understanding correct?