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Whitepaper - ARMv8-M Architecture Technical Overview

Joseph Yiu
Joseph Yiu
November 11, 2016
3 minute read time.

The next generation of ARM Cortex-M processors will be powered by a new architecture version called ARMv8-M architecture. This document provides a technical overview of various enhancements in the new architecture, as well as an introduction to the security technology, called TrustZone for ARMv8-M. This document also introduces AMBA 5 AHB5 which enables security management at a system level, and covers various use cases of the new technology.

ARMv8-M Architecture

  • ARMv8-M Architecture Technical Overview
  • ARMv8-M Architecture Reference manual

Information on ARMv8-M and TrustZone

  • The Next Steps in the Evolution of Embedded Processors for the Smart Connected Era
  • ARMv8-M architecture: what’s new for developers - YouTube

Cortex-M23, Cortex-M33 and Cortex-M35P processors information

  • Cortex-M | Introduction to ARM Cortex-M23 and Cortex-M33
  • Cortex-M23 processor product page
  • Cortex-M33 processor product page
  • Cortex-M35P processor product page
  • Cortex-M23 and Cortex-M33 - Security foundation for billions of devices
  • Five key features of the ARM Cortex-M23 Processor
  • Five key features of the ARM Cortex-M33 Processor
  • Cortex-M35P: multi-layered security at the heart of your device
  • Security principles for TrustZone for ARMv8-M (Webinar)

For details of Armv8.1-M processors (Cortex-M55, Cortex-M85), please visit:

      https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/cortex-m-resources

Resources for software developers

  • Documents on developer.arm.com

Topics

Document

Introduction

Introduction to the ARMv8‑M Architecture

TrustZone

TrustZone technology for ARMv8‑M Architecture

ARM C Language Extension (ACLE)

ACLE Extensions for ARMv8‑M

Secure software

Secure software guidelines for ARMv8‑M based platforms

System Design 

System Design for ARMv8-M

Exceptions and Interrupts

ARMv8‑M Exception Handling

Fault exception

Fault Handling and Detection

Power management and sleep modes

ARMv8-M processor power management secure state protection

Debug

ARMv8‑M Processor Debug

Memory model, MPU

Armv8-M Memory Model and MPU User Guide (doc, example codes)

MPU

Memory Protection Unit for ARMv8‑M based platforms

OS

RTOS design considerations for ARMv8‑M based platforms

ARMv8-M software development with ARM Compiler 6

Chapter 9 : Building Secure and Non-secure Images Using ARMv8-M Security Extensions

TrustZone software development in Keil MDK

Keil Application Note 291: Using TrustZone on ARMv8-M

Security extension details for compiler vendors

ARMv8-M Security Extension: Requirements on Development Tools (latest)

(v1.1)

ARMv8-M software development

EW2017 - Software Development on ARMv8-M Architecture

mbed(TM)OS deployment on Armv8-M

EW2017 - High-End Security Features for Low-End Microcontrollers

RTOS design

EW2019 - How RTOS should work in a TrustZone for Armv8-M environment

TrustZone Secure software

Stack sealing and why it is needed in TrustZone for Armv8-M

TrustZone Secure software Armv8-M processor Secure software Stack Sealing vulnerability
  • A few intricacies of writing ARMv8-M Secure code
  • Three ARM development tools to help you pioneer the IoT market
  • Security Extensions and Privilege Levels

Resources for silicon designers

  • Enhanced Security and Energy Efficiency of Microcontrollers and SoCs (AHB5 and Q channel introduction)
  • System Design for ARMv8-M
  • ARM AMBA 5 AHB Protocol Specification
  • AMBA APB Protocol Specification
  • AMBA Low Power Interface Specification
  • AMBA 4 ATB Protocol Specification
  • Corstone Foundation IP (Contains CoreLink SSE-200, CoreLink SIE-200 and more).
  • Webinar on secure system design
  • The six things you need to know about ARM CoreLink SSE-200 subsystem & ARM CoreLink SIE-200 system IP
  • CoreLink Interconnect | ARM CoreLink SIE-200 – ARM Developer
  • System Design | CoreLink SSE-200 subsystem – ARM Developer
  • Cortex-M Prototyping System+ (FPGA board)
Whitepaper - ARMv8-M Architecture Technical Overview.pdf
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  • Yasuhiko Koumoto
    Offline Yasuhiko Koumoto over 6 years ago

    Hello daith ,

    thank you for your detailed reply.

    I understood your comments as that the FPU lazy stacking was always enabled, and the stacking (if needed) would be done as the normal general registers. Also in the case of change from Secure to Non-Secure world, all the regsisters would be cleared.

    Is my understanding correct?

    Best regards,

    Yasuhiko Koumoto.

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  • Yasuhiko Koumoto
    Offline Yasuhiko Koumoto over 6 years ago

    Hello daith ,

    thank you for your detailed reply.

    I understood your comments as that the FPU lazy stacking was always enabled, and the stacking (if needed) would be done as the normal general registers. Also in the case of change from Secure to Non-Secure world, all the regsisters would be cleared.

    Is my understanding correct?

    Best regards,

    Yasuhiko Koumoto.

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