Your Q&A answered: How to implement a secure IoT system on Armv8-M

Last week we ran two packed webinars titled “How to implement a secure IoT system on Armv8-M”. During the webinar we looked at how to protect an IoT system from security attacks. We explored an example IoT system, showing all the necessary hardware and software components you need to consider in your next design. We also shared some of the products and tools available from Arm, to create the most efficient and viable IoT system.

During the webinar, we also announced the brand new Arm CoreLink SDK-200, which will help you accelerate your next IoT design. We even shared a unique discount code, which will allow you to access some best-in-class training from Arm experts, for just $99 – what a bargain!

Catch up now…

If you missed this technical webinar with Applications Engineer, Ed Player and IoT Product Manager, Mike Eftimakis – there’s still time to catch up! Just click the link below and start watching! The webinar was incredibly popular, so we promised to follow up with some of the questions we missed last week. Keep reading for the technical Q&A…

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Technical Q&A…

• Is the Arm CoreLink SSE-200 subsystem available for the Arm Cortex-M23?
• Why do you propose having two cores in your CoreLink SDK-200?
• How did you measure the Instruction cache efficiency? Just code execution from Flash? Reading data from Flash? Programming data to Flash?
• What sort of visibility does a non-secure debugger have of the secure sections? 
• Can secure accesses access both secure and nonsecure address map, whereas, nonsecure only access nonsecure part of the address map?
• At what point in time is the boot security map fixed into the chip?
• Does a library exist for Python to use the secure features of Armv8-M or can they only be accessed using ASM or C/C++?
• Is it possible to set a memory region from non-secure to secure at runtime?
• Will a BLXNS into a location which is marked as secure, end up in the non-secure state, or will there be an exception?
• Is the IDAU also run-time programmable?
• With regard to slide 38 that talks about calling from secure code to non-secure code, can we assume that the registers pushed {r4-r11} cannot be viewed by examining the stack?
• What is NSC?
• I didn't understand the difference between SAU and IDAU. Can you elaborate on it?
• Does Cortex-M33 support TCMs?
• What does Keil offer that GCC does not?
• Could you give some tips on developing for Armv8-M with IAR tools?