Virtual platform co-simulation is an advanced technique for accelerating SoC verification. The advantages are substantial and include earlier validation of hardware and software design assumptions, faster iteration of hardware and software changes and more efficient co-debug compared. Arm Fast Models have long been the golden reference models for the Arm architecture and these high-fidelity models make the ideal companion for co-simulation scenarios. In this blog we highlight the advantages of Avery Design Systems’ integration between Fast Models, Avery verification IP and the device under test. We’ll show how this integrated solution provides customers with an efficient and scalable SoC verification environment.
Through close collaboration with Arm, Avery Design Systems offers a virtual platform co-simulation solution for all Arm processors. The Avery solution provides complete hardware virtual platform to verify implementation of Arm-based designers earlier and comprehensively. Avery’s virtual platform co-simulation solution for Arm Fast Models supports connecting various Arm processors and virtual platform subsystems to SoC hardware captured at the Register Transfer Level to enable complete hardware and software system simulation. Key features added to the virtual platform include making it easier to perform hardware and software debug in a coordinated way. Users can run and control the execution of the hardware simulation and the software running on Arm Fast Models. By synchronizing the two environments and having effective hardware and software co-debug controls users can now see the complete state of the design. Visibility includes runtime memory or memory mapped registers in the software that are part of the SoC as well as hardware registers that reflect the current design status accessible with the debugger.
Avery’s virtual platform integration solution is based on interfacing the SystemC-based Arm virtual platform with the SystemVerilog simulation environment The SystemVerilog simulation may be running the SoC hardware testbench and AMBA VIPs, along with other verification IPs such as PCIe or ethernet. Users may run multiple virtual platforms simultaneously, for example, two embedded processors such as Cortex-R and Cortex-M and a Linux-based host server. Co-simulation is easy to setup and build for any kind of environment verification engineers require, either running on a single machine or communicating with the network environment.
Figure 1: Avery’s co-simulation solution connecting to local or network machine
In AMBA verification IPs, Avery supports a full set of bus protocols, from non-coherent to coherent, supports Requester and receiver models, interconnect models, and multi-protocol system-level interconnect and cache monitor for AMBA cache coherent protocols (ACE/CHI), CXL, and CCIX.
Figure 2: Topology for coherent protocols
A typical co-simulation environment consists of two virtual platforms, one being the X86 host server connecting PCIe/NVMe/CXL peripherals plugged into the virtual slot connector. Another might be the SoC’s embedded processing subsystem running OS or bare-metal code or firmware. The following diagram depicts the two virtual platforms and the HW RTL on the right side which is running in the SystemVerilog simulation. The RTL simulation side uses Avery’s VIPs (PCIe, CXL, AMBA) in passthrough mode. The Avery AVP adapter enables hooking into one and multiple virtual platforms into the overall co-simulation environment.
Figure 3: Example co-simulation setup
Avery and Arm have prepared the EVS_Cosim example to illustrate the full virtual platform and SystemVerilog co-simulation environment supporting versions of Cortex-A/R/M processors. The EVS_Cosim example and VIP licenses are available on request to firstname.lastname@example.org.
Figure 4: Block diagram of EVS_Cosim
To set up Avery’s co-simulation library for Arm-based designs, some simple steps are required:
In the SystemC process that is running the Arm Fast Model:
In the SystemVerilog process that is running Avery’s VIP and user design:
For a more detailed guide, please refer to the integration guide under $EVS_Cosim/Docs.
This debug topology not only applies on the Arm Fast Models <-> AXI co-simulation setup but applies to all Avery’s Virtual Platform (AVP) co-simulation system. The host can either be a QEMU simulating a x86 platform and have PCIe/NVMe/CXL peripheral exported to SystemC, or an Arm Fast Models exporting amba_pv initiator/target and legacy interrupt pin. The debugging log going in and out of Avery’s adapter provide transparent view of the traffic which is not always possible using the hardware platform.
Figure 5: Illustration of agent printing debug information
Avery provides text debug at both the SystemC transactor side and SystemVerilog AXI device. The Arm box shows all traffic coming from the Arm Fast Models. The AMBA manager/subordinate box shows Avery’s AXI Verification IP debug tracker file, which is more AXI specification specific. This should provide enough transparency for users to observe all the traffic that is coming out or going into the Fast Models and coming out or going into their RTL design that connects to Avery’s Verification IP.
Figure 6.1: Co-simulation running with GDB Figure 6.2: Debug log printed by System C adapter
Note that Avery’s Verification IP environment is identical with Avery’s traditional IP verification approach. This means it is interchangeable with traditional UVM verification approaches, enabling users to write their own sequencer to generate the same traffic. This allows users to replicate the errors or bugs encountered using the Arm Fast Models running their in-house firmware.
Figure 7: Debug log printed by AXI VIP
Taking existing SystemVerilog testbench and UVM Verilog VIP, if one of the peripherals is supported by Avery’s Virtual Platform solution, we can run the embedded firmware on Arm Fast Models to generate traffic, facilitating hardware and software co-debug. The co-simulation is lightweight and easy to use, and is inter-swappable with conventional Avery IP verification environment, so users can reproduce the scenario in pure SystemVerilog without making any modification on the RTL testbench. The performance is 10^4 compared to logic simulation of a full or partial hardware module running in SystemVerilog/Verilog. Users can also debug the firmware running in the Fast Models using the GDB remote plug-in provided by Arm, versus an FPGA setup, where users read register values using a JTAG and UART. The former approach brings more clarity while still having the firmware participating in the simulation. Avery’s Virtual Platform solution increases the overlap time between RTL design and firmware development to enable users to spot issues earlier, speed up the development cycle and cut down development cost.
Getting a leg up on system verification at early RTL and embedded SW stages benefit design teams in three key ways:
Avery virtual platform co-simulation environment supports all simulator vendors and is optimized for best runtime performance.