Musings about Moore's Law and future technology

     Photo modified by Greg Yeric from original by Eric Fischer.

I was recently invited to add some thoughts on technology scaling over at Ed Sperling's excellent semiengineering site.   Here is what I came up with:

What Goes Around Comes Around:   Moore's Law at 10nm and Beyond

The gist of my article is captured in the (slightly altered) photo above:   For an incredibly long time, chip designs have benefited from the amazing progress that is Moore's Law, and then by association Dennard scaling.   It's been kind of like 49 years of being able to use an escalator, but now we find that convenience we've come to expect isn't working and now we have to use the stairs.   And by "we" I mean designers in concert with semiconductor technologists, in an exercise often termed Design-Technology Co-Optimization.  DTCO is one of the areas of our R&D group here at ARM, and I talk about some specific technology scaling issues in the article.    

I was running a little tight on space for the article, and given the readership over at Semiengineering, I took the liberty to use a number of terms without defining them very well.   Give it a read, and send me a question if something is not clear.  As this is my first post on the ARM Connected Community, I'll be endeavoring from here on out to keep providing information along these lines, and about semiconductor technology trends in general, but here I'll take the time to explain things a bit better.   Just like systems engineers have to slow down when they talk to me .

"cheers" (that's in the article)

- Greg