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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 729 Questions
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  • Not Answered

    Arm FVP and continuous integration 0

    2465 views
    1 reply
    Latest over 5 years ago
    by Daniel Owens Arm Employee Badge
  • Answered

    Arm FVP on CI +1

    • AEMv8 FVP
    • Fixed Virtual Platforms (FVPs)
    2608 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Design considerations for implementing flash program download 0

    • CoreSight Architecture
    • SWD
    • Debug Access Port (DAP)
    15850 views
    3 replies
    Latest over 5 years ago
    by Mohamed Nasser
  • Not Answered

    Using sram instead of a flash memory in ASIC implementation 0

    • SoC Implementation
    • SRAM
    • SoC FPGA
    • Debugging
    8650 views
    0 replies
    Started over 5 years ago
    by Mohamed Nasser
  • Not Answered

    Behaviour of CHI Receiver during race condition from RUN to DEACTIVATE 0

    • AMBA
    • AMBA 5 CHI
    • CHI
    • Bus Architecture
    • AMBA 5
    9011 views
    0 replies
    Started over 5 years ago
    by amit
  • Not Answered

    In APB, Why do we use enable signal? (Don't care about PREADY) 0

    8936 views
    0 replies
    Started over 5 years ago
    by INNS
  • Answered

    Warning : #167-D - for function sprintf +1

    3967 views
    2 replies
    Latest over 5 years ago
    by Oleg Nicolaiciuc
  • Not Answered

    DC/DC Controller SoC 0

    9755 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Answered

    Read data from a csv file +1

    • Keil
    • file
    3129 views
    1 reply
    Latest over 5 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    AMBA 5 CHI : Does Interleaving of TxnID within a Multiple flits message allowed? +1

    • System on Chip (SoC)
    • AMBA 5 CHI
    • CHI
    • Cache Architecture
    10954 views
    1 reply
    Latest over 5 years ago
    by IPDeveloper
  • Not Answered

    AXI4 transaction attributes 0

    9250 views
    0 replies
    Started over 5 years ago
    by Ravi V.
  • Answered

    AMBA 5 CHI Link Layer (L-Credit Return) 0

    • AMBA 5 CHI
    • CHI
    • Cache Coherent Interconnect
    • AMBA 5
    15174 views
    3 replies
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    cortex-r52 integer divide support 0

    4176 views
    4 replies
    Latest over 5 years ago
    by Jahnavi_Guvvala
  • Answered

    Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model? 0

    • AXI4
    13851 views
    1 reply
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Signal deadlock in linting 0

    1586 views
    0 replies
    Started over 5 years ago
    by Janarthanam R S
  • Answered

    MPAM cache partitioning support in FVP base model 0

    • Cache
    • Armv8-A
    • Fixed Virtual Platforms (FVPs)
    4153 views
    3 replies
    Latest over 5 years ago
    by Matteo Zini
  • Not Answered

    BUSY transfer just before the last transfer in a burst by a AHB Master. 0

    12686 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    AMBA AXI reset 0

    • AMBA
    • AXI
    22020 views
    3 replies
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    strobe 0

    17452 views
    3 replies
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Enabling top-byte ignore on ARMv8 Base FVP 0

    • AEMv8 FVP
    • Architecture
    • Armv8-A
    • Fixed Virtual Platforms (FVPs)
    3652 views
    3 replies
    Latest over 5 years ago
    by Mohannad Ismail
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Topics being discussed in this forum
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  • AHB
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