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SoC Design and Simulation forum AHB DeadLock: HREADY=0 & HTRANS=BUSY

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AHB DeadLock: HREADY=0 & HTRANS=BUSY

Chanpreet Singh over 4 years ago

If the slave asserts wait state (HREADY=0), and master asserts HTRANS =BUSY, then should the slave wait for change of HTRANS from BUSY to NONSEQ/SEQ or should the slave change the HREADY=1. This condition happens at 'Incrementing burst of undefined length'. This is a deadlock condition; something which is not clear from AHB spec.

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Colin Campbell over 4 years ago +1 verified

This isn't a deadlock. The slave's data phase HREADY=0 response is for the previous address phase transfer (which must have been a NONSEQ or SEQ transfer), and is not in any way related to the current...

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0 Oliver Beirne over 4 years ago

Hi Chanpreet Singh

Just for your information I have moved your thread to the SoC forum where it should live.

Thanks!
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0 Oliver Beirne over 4 years ago

Hi Chanpreet Singh

Just for your information I have moved your thread to the SoC forum where it should live.

Thanks!
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