We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
If the slave asserts wait state (HREADY=0), and master asserts HTRANS =BUSY, then should the slave wait for change of HTRANS from BUSY to NONSEQ/SEQ or should the slave change the HREADY=1. This condition happens at 'Incrementing burst of undefined length'. This is a deadlock condition; something which is not clear from AHB spec.
Hi Chanpreet Singh
Just for your information I have moved your thread to the SoC forum where it should live.
Thanks!