Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
SoC Design and Simulation forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 735 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • TOSA forum

  • Suggested Answer

    outstanding transaction in AXI4 protocol 0

    15983 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Aligned and unaligned word transfers on a 64-bit bus +1

    • AXI
    • AXI4
    28451 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Lock Signal for AXI Slave +1

    • AXI
    17911 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Request for advise on better ARM learning path for VLSI engineer 0

    • FPGA
    16566 views
    2 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Fast model : Is there any way to overwrite PVBUS master id without using components which have id parameter (e.g. master_id, cluster_id ) 0

    • Fast Models
    15312 views
    1 reply
    Latest over 6 years ago
    by Jon Black Arm Employee Badge
  • Suggested Answer

    The meanings of AxCACHE 0

    19872 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    CoreLink NIC-400 Interconnect gives an extra request 0

    • CoreLink NIC-400 Network Interconnect
    15529 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Is there a limit for AXI4 outstanding transaction? 0

    • AXI4
    21289 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    How can I produce SID code for transfer data in radio modems? 0

    13320 views
    0 replies
    Started over 6 years ago
    by M.Rahnama
  • Not Answered

    Choose ARM 0

    13140 views
    0 replies
    Started over 6 years ago
    by MED-AMINE
  • Answered

    why PSTRB signal in APB4 have four bits? +1

    • APB
    • AMBA
    • AMBA 4
    27874 views
    4 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    what is unaligned address access? 0

    23051 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    AXI data channel 0

    13844 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    I have a question about the destination of HWRITE data signal. 0

    13965 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Basic Understanding for AXI WRITE INCR +1

    • AMBA 3 AXI Interface
    • AXI
    19498 views
    2 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data 0

    • Embedded
    • SRAM Memory
    • Embedded Trace Macrocell
    • CoreSight
    • Debug and Trace
    • Memory
    16969 views
    2 replies
    Latest over 6 years ago
    by jeremy_ng
  • Answered

    How is the PREADY signal triggered low by the Slave in an APB? +1

    • APB
    • AMBA 3
    • Bus Architecture
    15356 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    what action will be performed by the master based on the read and write responce in axi 4? 0

    • AXI
    • AXI4
    15835 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    ACE protocol : Eviction and snoop request at same time +1

    • AMBA
    • L1
    • ACE
    • Cache
    16217 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    AXI3 write data interleaving with same AWID +1

    • AMBA
    • AXI
    19196 views
    4 replies
    Latest over 6 years ago
    by mveereshm622
<>
Topics being discussed in this forum
  • ACE
  • AEMv8 FVP
  • AHB
  • AHB5
  • AHB-Lite
  • AMBA
  • AMBA 5
  • AMBA 5 CHI
  • APB
  • Arm Development Studio
  • Armv8-M
  • AXI
  • AXI4
  • Bus Architecture
  • CHI
  • CoreLink NIC-400 Network Interconnect
  • CoreSight
  • Cortex-A
  • Cortex-M
  • DesignStart
  • Fast Models
  • Fixed Virtual Platforms (FVPs)
  • Interface
  • socrates
  • TrustZone