Hi there,
good morning.
I am using TMC as Embedded Trace Fifo and testing it for FULL condition.
Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF?
So that eventually it gets full setting the FULL bit in STS register.
I can see that none of the Flushing choices are enabled in FFCR register.
But still I can see that the memory is being read as soon as data is put in it.
Thus it always remains empty and I cant get it filled up completely.
Attached TRM is having one state machine on page 30 showing where all trace data can be dumped out of TMC.
But doesn't really help since the TraceCaptEn is high throughout the simulation and TMCReady bit always remains low.
And form what I understand is that while the FSM is in Running or Stopping state it already reads the date form SRAM memory.
Which is kind of bizarre and makes no sense to me.
Any help will be appreciated. The TRM on TMC is very vague and not at all helpful.
Thanks.
Hi Sir, i will like to ask how can one modify the values of the mode register?
I have been trying to write to register directly through devmem but it reads the old value as soon as it writes the new value
135|hikey960:/ # devmem2 0xec036028 w 0x2 /dev/mem opened. Memory mapped at address 0x75302e7000. Value at address 0xEC036028 (0x75302e7028): 0x0 Written 0x2; readback 0x0
0xec036000 is the address of my ETF driver. Looking at the documentation on TMC [DDI0461B - tmc] I know that the mode register is 0x28 bytes offset from my base address. However, attempts to write is futile as it returns the old value (Circular Buffer mode).
I also cannot make any changes to the mode file in /sys/bus/coresight/devices/*.etf/mgmt/mode. I have been trying to work on this for the past 4 weeks but to poor results.
Any assistance and guidance on this matter will be greatly appreciated!