Aligned and unaligned word transfers on a 64-bit bus

Although the AXI protocol describes itself as supporting unaligned transfers, it really is still working in an aligned manner. So each transfer in a transaction still needs to work within an AxSIZE aligned range of byte lanes.

Where you have this example transaction, the "aligned" start address is 0x4 (AxSIZE signals a 32-bit transfer, so 0x4 is the 32-bit aligned equivalent of AxADDR=0x7). Start address 0x7 means that only D[63:56] of the 32-bit D[63:32] range of bits of the 64-bit data bus can be used for this "unaligned" start address.

But after this first transfer all further transfers in the INCR burst ARE fully aligned, so the second transfer is to "aligned start address" (0x4) plus "AxSIZE=32-bit" address increment (0x4 bytes), meaning the second transfer is to 0x8.

AxSIZE, the "transfer size", tells you by how much the address will increment for each transfer in the INCR transaction, so transfers to 0x4 (the aligned version of 0x7), then 0x8, then 0xC and finally 0x10.

Each transfer after the first transfer is to an AxSIZE aligned address, so the "unligned" behaviour only applies to just this first transfer in this INCR burst.

If the burst type had been "FIXED", every transfer in the FIXED burst would remain "unaligned" to that same start address.