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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 739 Questions
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  • Suggested Answer

    In case of AXI4 lite protocol,what is the relation between BValid signal and Wvalid signal? 0

    • AXI4-Lite
    • AMBA
    • Interface
    17188 views
    4 replies
    Latest over 7 years ago
    by Nitin Dixit
  • Answered

    AXI WVALID before AWVALID 0

    • AMBA
    • AXI
    • Interface
    10924 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    I didn't understand the difference between SAU and IDAU. Can you elaborate on it? +1

    • TrustZone
    • Armv8-M
    16852 views
    4 replies
    Latest over 7 years ago
    by Andreas Papaliolios
  • Suggested Answer

    chi protocol 0

    • AMBA
    • CHI
    10222 views
    1 reply
    Latest over 7 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    unaligned address in AXI protocol 0

    • AMBA
    • AXI
    • AXI4
    15473 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Project on AXI Bus. 0

    • AMBA
    • AXI
    • Bus Architecture
    7776 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Regarding WRAP burst calculation in AXI4 0

    • AMBA
    • AXI4
    • Interface
    8582 views
    2 replies
    Latest over 8 years ago
    by pavan316
  • Not Answered

    Flashing STM32L0 0

    • stm32cube
    • Cortex-M0
    • APB Peripherals
    • Cortex-M
    • PrimeCell UART (PL011)
    7212 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    AXI modifiable read access 0

    • AMBA
    • AXI
    • AXI4
    10746 views
    2 replies
    Latest over 8 years ago
    by arc
  • Suggested Answer

    MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave +1

    • AMBA
    • PrimeCell Color LCD Controller (PL111)
    • AMBA AHB Controllers
    • AHB
    11627 views
    3 replies
    Latest over 8 years ago
    by Logicallyfit
  • Not Answered

    amba ahb 0

    • AMBA
    • AHB
    • Interface
    8824 views
    4 replies
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    HRESP 0

    • AMBA
    • AHB
    • Interface
    6359 views
    1 reply
    Latest over 8 years ago
    by Vanhealsing
  • Suggested Answer

    AMBA AHB 0

    • AMBA
    • AHB
    • Interface
    7566 views
    1 reply
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    why we need write strobe in axi 0

    • AMBA
    • AXI
    • Interface
    13703 views
    2 replies
    Latest over 8 years ago
    by verifengg
  • Not Answered

    AXI read reordering depth and read interleaving depth. Are they same?AXI +1

    • AMBA
    • AXI
    • Interface
    12840 views
    1 reply
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Cache in SOCs 0

    • Cache
    9088 views
    4 replies
    Latest over 8 years ago
    by Ahmed Zafar
  • Answered

    ARM AXI4 protocol assertions trigger errm_wdata_num_prop5 and errm_wlast_stable quesitons 0

    • AMBA
    • AXI
    • AXI4
    11281 views
    4 replies
    Latest over 8 years ago
    by armchronos
  • Not Answered

    AXI WRITE DATA CHANNEL 0

    • AMBA
    • AXI
    • Interface
    11154 views
    2 replies
    Latest over 8 years ago
    by Muthu_venkatesh
  • Not Answered

    Why do AMBA AXI does not support AxBURST of decrementing address type? 0

    • AMBA
    • AXI
    • Interface
    6021 views
    1 reply
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    AHB wait state insertion 0

    • AMBA
    • AHB
    • Interface
    15039 views
    7 replies
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
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