Hi ARM/arktos,
Seems like this online discussion is not working properly.
I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.
So most likely you may not see it.
Below is my reply to your answer to my question.
Thanks for the detailed reply !!
It's quite helpful to understand the usage purposes of these signals.
But need clarification about the generation of AWAKEUP and ACWAKEUP.
Sounds like you can logically OR the AWVALID/ARVALID/WVALID and add a register pipeline to delay the normal AXI signals
to generate AWAKEUP.
For ACWAKEUP which comes from the interconnect, one may similarly directly connect ACWAKEUP from ACVALID and register pipeline the ACE5 signals to ensure ACWAKEUP comes at least one cycle before ACVALID.
From the AMBA 5 spec, it seems like AWAKEUP, ACWAKEUP, VAxQOSACCEPT, SYSO* are REQUIRED signals. Please confirm.
Also, these new signals are not associated other signals such as a handshake. So they are independent of regular AXI/ACE signals
but the user needs to ensure the proper state of these signals in relation to AXI/ACE signals at the SYSTEM or SOC level.
Only the VAxQOSACCEPT behave like static register signals but need to still be synchronized to the AXI/ACE clock.
Please confirm my understanding or correct it.
Thanks,
David
Hi David,
I posted an answer to this over in https://community.arm.com/soc/f/discussions/9904/please-explain-some-of-the-new-ace5-signals-in-relation-to-the-master-and-interconnect-behavior