Hi,
I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work?
Are you trying to add an AXI master or AXI slave ?
Does the existing architecture already have connections for you to add that master or slave, or do you also need to modify the architecture ?
Assuming you are trying to add an AXI slave, the simplest project would be something like an internal SRAM interface, so just converting each AXI transfer into an SRAM timed access, and adding some sort of logic to handle when you get coincident read and write accesses (which do you respond to first).
If you are looking for something more interesting or less simple, starting with this simple SRAM model then gives you something to adapt, once you get the initial interface function working.
Perhaps someone can suggest something more interesting if that is your aim.