chi protocol

So simplifying and ignoring some of the corner cases a little:

For most accesses, a master needs to receive a Comp response from the interconnect in order to guarantee that a transaction is ordered with respect to later transaction.

When we say 'ordered with respect to', what we really mean is that if you send another transaction after this one, the later transaction cannot overtake or occur before the previous one.

Depending on the memory type being targeted, the range of addresses that this ordering applies to will change.  For example, for Cacheable memory, this ordering only applies to the same location.

A master can then set additional flags on transactions to apply specific ordering requirements for certain transactions, which would give better performance than waiting for the Comp response - see Section 7.4.

So simplifying and ignoring some of the corner cases a little:

For most accesses, a master needs to receive a Comp response from the interconnect in order to guarantee that a transaction is ordered with respect to later transaction.

When we say 'ordered with respect to', what we really mean is that if you send another transaction after this one, the later transaction cannot overtake or occur before the previous one.

Depending on the memory type being targeted, the range of addresses that this ordering applies to will change.  For example, for Cacheable memory, this ordering only applies to the same location.

A master can then set additional flags on transactions to apply specific ordering requirements for certain transactions, which would give better performance than waiting for the Comp response - see Section 7.4.