Hi All,
I have doubt in ahb_lite hresp signaling when the address phase is extending.
In the following diagram transfer address c is extending because of data phase of B.
In 3rd clk cycle address C is sampled so that shall we expect the hresp on 4th clk cycle or 5 th clk cycle.
But data for address C is sampling in 5 th clk cycle .
Please some one explain the relation for the hresp signal ....
Is it only related with haddr or haddr and hready also ?
Thanks & Regards
Muthuvenkatesh