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AHB Lite Response

Muthuvenkatesh

Hi All,

                           I have doubt in ahb_lite hresp signaling when the address phase is extending.

In the following diagram transfer address c is extending because of data phase of B.

In 3rd clk cycle address C is sampled so that shall we expect the hresp on 4th clk cycle or 5 th clk cycle.

But data for address C is sampling in 5 th clk cycle .

Please some one explain the relation for the hresp signal ....

Is it only related with haddr or haddr and hready also ?

Thanks & Regards

Muthuvenkatesh

Parents
  • +1

    From ARM AMBA 5 AHB Protocol Specification (AHB5, AHB-Lite)

    Chapter 5.1 Slave transfer responses

    HRESP (signal direction -> from slave to master)

    0        OKAY         (normal transfer)

    1        ERROR     (error during transfer)

    HRESP relates to HREADY (which is used by slave to inform master about extended transfer):

    HRESP   HREADY   transfer type

    0             0                pending transfer

    0             1                successful transfer completed

    1             0                error response, first cycle

    1             1                error response, second cycle

Reply
  • +1

    From ARM AMBA 5 AHB Protocol Specification (AHB5, AHB-Lite)

    Chapter 5.1 Slave transfer responses

    HRESP (signal direction -> from slave to master)

    0        OKAY         (normal transfer)

    1        ERROR     (error during transfer)

    HRESP relates to HREADY (which is used by slave to inform master about extended transfer):

    HRESP   HREADY   transfer type

    0             0                pending transfer

    0             1                successful transfer completed

    1             0                error response, first cycle

    1             1                error response, second cycle

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