Hi,
In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)
I wanted to know if this a valid scenario or a protocol violation?
Also is there any relation between Hsel assertion and Hmaster toggling?