Hi,
In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)
I wanted to know if this a valid scenario or a protocol violation?
Also is there any relation between Hsel assertion and Hmaster toggling?
HSEL is an address phase signal, and should be a combinatorial logic decode of HADDR MSBs, so it could change during the data phase of your transfer if the master is next not addressing your slave.
Note that one problem with your waveform is that HSEL appears to be generated on HCLK falling edges. All AHB activity should be based only on HCLK rising edges !
HMASTER indicates the active master number. It is address phase aligned, just like HADDR and so HSEL. However there is no relation between HSEL assertion and HMASTER as a master can remain active on the bus, but not always accessing one particular slave.